AD8420ARMZ-R7 datasheet(20/27 Pages) AD

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Data Sheet

AD8420

Rev. A | Page 19 of 26

THEORY OF OPERATION

+IN

–IN

gm1

+VS

–VS

+VS

–VS

+VS

–VS

VOUT

REF

AD8420

gm2

ESD

PROTECTION

ESD

PROTECTION

Figure 58. Simplified Schematic

ARCHITECTURE

The AD8420 is based on an indirect current feedback topology

consisting of three amplifiers: two matched transconductance

amplifiers that convert voltage to current and one integrator

amplifier that converts current to voltage.

For the AD8420, assume that all initial voltages and currents are

zero until a positive differential voltage is applied between the

inputs, +IN and −IN. Transconductance Amplifier gm1 converts this

input voltage into a current, I1. Because the voltage across gm2 is

initially zero, I2 is zero and I3 equals I1.

I3 is integrated to the output, making the output voltage, VOUT,

increase. This voltage continues to increase until the same differ-

ential input voltage across the inputs of gm1 is replicated across

the inputs of gm2, generating a current (I2) equal to I1. This reduces

the Difference Current I3 to zero so that the output remains at a

stable voltage. The gain in the configuration shown in Figure 58 is

set by R2 and R1.

In traditional instrumentation amplifiers, the input common-

mode voltage can limit the available output swing, typically

depicted in a hexagon plot. Because the AD8420 converts the

input differential signals to current, this limit does not apply. This

is particularly important when amplifying a signal with a common-

mode voltage near one of the supply rails.

To improve robustness and ease of use, the AD8420 includes

differential voltage protection to limit the current into its inputs

to a safe level. This protection scheme allows wide differential

input voltages without damaging the device.

SETTING THE GAIN

The transfer function of the AD8420 is

VOUT = G(V+IN − V−IN) + VREF

where



 1

Table 7. Suggested Resistors for Various Gains, 1% Resistors

R1 (kΩ)

R2 (kΩ)

Gain

None

Short

1.00

49.9

2.00

80.6

5.03

90.9

10.09

95.3

20.06

97.6

49.8

100

101

200

201

499

500

1000

1001

While the ratio of R2 to R1 sets the gain, the designer determines

the absolute value of the resistors. Larger values reduce power

consumption and output loading; smaller values limit the FB input

bias current and offset current error. For best output swing and

distortion performance, keep (R1 + R2) || RL ≥ 20 kΩ.

A method that allows large value feedback resistors while limiting

FB bias current error is to place a resistor of value R1 || R2 in

series with the REF terminal, as shown in Figure 59. At higher

gains, this resistor can simply be the same value as R1.

AD8420

+IN

–IN

REF

VOUT

G = 1 +

IB+

IB–

VREF

||R2

–

IBR

IBF

Figure 59. Cancelling Out Error from FB Input Bias Current

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