AD8420ARMZ-R7 datasheet(22/27 Pages) AD

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Data Sheet

AD8420

Rev. A | Page 21 of 26

LAYOUT

Common-Mode Rejection Ratio over Frequency

Poor layout can cause some of the common-mode signal to be

converted to a differential signal before reaching the in-amp. This

conversion can occur when the path to the positive input pin

has a different frequency response than the path to the negative

input pin. For best CMRR vs. frequency performance, the input

source impedance and capacitance of each path should be closely

matched. This includes connecting Pin 1 to −VS, which matches the

parasitic capacitance and the leakage between the inputs and

adjacent pins. Place additional source resistance in the input

path (for example, for input protection) close to the in-amp inputs

to minimize their interaction with the parasitic capacitance from

the printed circuit board (PCB) traces.

Power Supplies

Use a stable dc voltage to power the instrumentation amplifier.

Noise on the supply pins can adversely affect performance. For

more information, see the PSRR performance curves in Figure 24

and Figure 25.

Place a 0.1 μF capacitor as close as possible to each supply pin.

As shown in Figure 62, a 10 μF tantalum capacitor can be used

farther away from the device. This capacitor, which is intended

to be effective at low frequencies, can usually be shared by other

precision integrated circuits. Keep the traces between these

integrated circuits short to minimize interaction of the trace

parasitic inductance with the shared capacitor.

AD8420

+VS

+IN

–IN

0.1µF

10µF

0.1µF

10µF

–VS

VOUT

Figure 62. Supply Decoupling, REF, and Output Referred to Local Ground

Reference

The output voltage of the AD8420 is developed with respect to

the potential on the reference terminal. Take care to tie REF to the

appropriate local ground. The differential voltage at the inputs is

reproduced between the REF and FB pins; therefore, it is important

to set VREF so that the voltage at FB does not exceed the input range.

DRIVING THE REFERENCE PIN

Traditional instrumentation amplifier architectures require the

reference pin to be driven with a low impedance source. In these

architectures, impedance at the reference pin degrades both CMRR

and gain accuracy. With the AD8420 architecture, resistance at

the reference pin has no effect on CMRR.

AD8420

+IN

–IN

REF

VOUT

G = 1 +

R2 + RREF

VREF

RREF

Figure 63. Calculating Gain with Reference Resistance

Resistance at the reference pin does affect the gain of the AD8420,

but if this resistance is constant, the gain setting resistors can be

adjusted to compensate. For example, the AD8420 can be driven

with a voltage divider to level shift the output as shown in

Figure 64.

AD8420

+IN

–IN

REF

VOUT

G = 1 +

R2 + R3

||R4

Figure 64. Using Resistor Divider to Set Reference Voltage

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