AD8556ACPZ-R2 datasheet(20/28 Pages) AD

20 / 28 page

Data Sheet

AD8556

OPEN WIRE FAULT DETECTION

The inputs to A1 and A2, VNEG and VPOS, each have a com-

parator to detect whether VNEG or VPOS exceeds a threshold

voltage, nominally VDD − 2.0 V. If (VNEG > VDD − 2.0 V) or

(VPOS > VDD − 2.0 V), VOUT is clamped to VSS. The output

current limit circuit is disabled in this mode, but the maximum

sink current is approximately 10 mA when VDD = 5 V. The inputs

to A1 and A2, VNEG and VPOS, are also pulled up to VDD by

currents IP1 and IP2. These are both nominally 49 nA and

matched to within 3 nA. If the inputs to A1 or A2 are accidentally

left floating, as with an open wire fault, IP1 and IP2 pull them

to VDD, which would cause VOUT to swing to VSS, allowing

this fault to be detected. It is not possible to disable IP1 and IP2,

nor the clamping of VOUT to VSS, when VNEG or VPOS

approaches VDD.

SHORTED WIRE FAULT DETECTION

The AD8556 provides fault detection when VPOS, VNEG, or

VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage

regions at VPOS, VNEG, and VCLAMP that trigger an error

condition. When an error condition occurs, the VOUT pin is

shorted to VSS. Table 8 lists the voltage levels shown in Figure 48.

VPOS

VNEG

VSS

VINL

VINH

VDD

VSS

VCLL

VDD

VCLAMP

VSS

VINL

VINH

VDD

ERROR

NORMAL

ERROR

NORMAL

ERROR

NORMAL

Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP

that Trigger a Fault Condition

Table 8. Typical VINL, VINH, and VCLL Values (VDD = 5 V)

Voltage

Min (V)

Typ (V)

Max (V)

VOUT Condition

VINH

2.95

3.0

3.05

Short to VSS fault

detection

VINL

1.95

2.0

2.05

Short to VSS fault

detection

VCLL

1.05

1.1

1.15

Short to VSS fault

detection

FLOATING VPOS, VNEG, OR VCLAMP FAULT

DETECTION

A floating fault condition at the VPOS, VNEG, or VCLAMP

pins is detected by using a low current to pull a floating input

into an error voltage range, defined in the Shorted Wire Fault

Detection section. In this way, the VOUT pin is shorted to VSS

when a floating input is detected. Table 9 lists the currents used.

Table 9. Floating Fault Detection at VPOS, VNEG, and

VCLAMP

Mnemonic

Typical Current

Goal of Current

VPOS

49 nA pull-up

Pull VPOS above VINH

VNEG

49 nA pull-up

Pull VNEG above VINH

VCLAMP

0.2 µA pull-down

Pull VCLAMP below VCLL

DEVICE PROGRAMMING

Digital Interface

The digital interface allows the first stage gain, second stage

gain, and output offset to be adjusted and allows desired values

for these parameters to be permanently stored by selectively

blowing polysilicon fuses. To minimize pin count and board

space, a single-wire digital interface is used. The digital input pin,

DIGIN, has hysteresis to minimize the possibility of inadvertent

triggering with slow signals. It also has a pull-down current sink

to allow it to be left floating when programming is not being

performed. The pull-down ensures inactive status of the digital

input by forcing a dc low voltage on DIGIN.

A short pulse at DIGIN from low to high and back to low again,

such as between 50 ns and 10 µs long, loads 0 into the shift register.

A long pulse at DIGIN, such as 50 µs or longer, loads 1 into the

shift register. The time between pulses should be at least 10 µs.

Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 ×

VDD are recognized as a low, and voltages at DIGIN between

0.8 × VDD and VDD are recognized as a high. The timing

diagram example in Figure 49 shows the waveform for entering

code 010011 into the shift register.

Rev. B | Page 19 of 27

AD8556ACPZ-R2 数据表(PDF) 20 Page - Analog Devices

AD8556ACPZ-R2 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

AD8556ACPZ-R2 数据表(PDF) 20 Page - Analog Devices

AD8556ACPZ-R2 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载