Data Sheet

ADLD8403

THEORY OF OPERATION

A Class H DSL line driver achieves power savings by using

internally developed, signal tracking, power supplies. These

supply of 12.5 V nominal. The power savings occur due to

minimum headroom provided by the tracking, or pumped,

supplies to ensure nonsaturation of the output buffer amplifier.

For Class H drivers, the average total power that the amplifier

consumes is lower than that of conventional Class AB amplifier

architectures using a fixed supply.

The ADLD8403 is the second implementation of a patented

amplifier architecture developed by Analog Devices. This new

architecture, known as Adaptive Linear Power (ALP), is optimized

to process signals with occasional peaks that are much greater than

the rms level, such as the discrete multitone (DMT) signals used

in xDSL applications. Figure 11 shows the ADLD8403 block

diagram. Included are two Class AB current feedback (CFB)

amplifiers, along with the ALP unit and standard bias block.

The architecture combines Class AB amplifiers with the ALP to

provide a system that generates internal supplies (VCCP and

VEEP) that move linearly with the input signal. This movement is

achieved by sampling the input signal via the input pins, INPA and

INNA, and applying the appropriate gain to create the variable

supplies at the VCCP and VEEP pins.

The ADLD8403 contains two complete channels of ADSL2+

compliant drivers. Each channel has a power mode signal, or

PD pin (PD_A and PD_B), that enables the output buffer.

Additionally, in applications where less than 14.5 dBm of line

power is required, a third PD_PMP signal is used to disable the

signal tracking, power supplies. This feature reduces power

consumption by approximately 125 mW for these reduced line

powers. Because both channels share the pumped supplies in

the ADLD8403, the PD_PMP pin is used only when both

channels require less than 14.5 dBm of line power.

The ADLD8403 is intended for use in digital subscriber line

access multiplexor (DSLAM) applications. The ADLD8403 a

simple process and allows for ease of upgrading existing DSLAM

systems.

VCC

4kΩ

4kΩ

+

–

VOPA

INPA

VCOM_A

INNA

VONA

CFB

CFB

BIAS

ALP

PD_A

PD_PMP

VCC

CAPP

VCCP

CAPN

VEEP

GND

Figure 11. Block Diagram

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