AD8505/AD8506/AD8508

Rev. E | Page 17 of 20

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-178-AA

10°

5°

0°

SEATING

PLANE

1.90

BSC

0.95 BSC

0.20

BSC

5

12

3

4

3.00

2.90

2.80

3.00

2.80

2.60

1.70

1.60

1.50

1.30

1.15

0.90

0.15 MAX

0.05 MIN

1.45 MAX

0.95 MIN

0.20 MAX

0.08 MIN

0.50 MAX

0.35 MIN

0.55

0.45

0.35

Figure 51. 5-Lead Small Outline Transistor Package [SOT-23]

(RJ-5)

Dimensions shown in millimeters

0.40 BSC

0.80

BSC

1.425

1.385

1.345

0.945

0.905

0.865

SEATING

PLANE

0.645

0.600

0.555

0.415

0.400

0.385

0.40

BSC

A

1

2

B

C

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

BALL A1

IDENTIFIER

0.05 NOM

COPLANARITY

0.230

0.200

0.170

0.287

0.267

0.247

Figure 52. 6-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-6-7)

Dimensions shown in millimeters