ADP2360

Data Sheet

Rev. 0 | Page 10 of 15

THEORY OF OPERATION

SW

POWER GOOD

COMPARATOR

COMPARATOR

FEEDBACK

COMPARATOR

ZERO CROSSING

DETECTOR

COMPARATOR

VIN

BAND GAP

BG

0.8V

4

3

1µA

ITH

SS

FB

R1

R2

L1

7

1

AGND

EN

ADP2360

9

VREG

8

UVLO

0µA TO

5µA

0.8V

TSD

TSD

LEVEL

SHIFT

CONTROL

LOGIC

UVLO

TSD

2

4

FB

R1

R2

ENABLE

CONTROL

PGND

6

UVLO

VREG

ADJUSTABLE OUTPUT

VOLTAGE

FIXED OUTPUT

VOLTAGE

PG

5

NOTES

1. THE PORTIONS IN THE DASHED BOXES DISPLAY THE DIFFERENCE OF THE FUNCTIONALITY OF PIN 4

FOR THE ADJUSTABLE AND FIXED OUTPUT VOLTAGES.

Figure 21. Block Diagram

OVERVIEW

The ADP2360 is a high efficiency, high input voltage, DCM

synchronous, step-down, dc-to-dc switching regulator.

The ADP2360 uses a single-pulse PFM architecture with adjustable

and to minimize the input and output ripple.

The ADP2360 further offers a power-good (PG) pin with an

open-drain output signal to indicate when the output voltage is

stable. Other key features include 100% duty cycle operation,

precision enable control, external soft start control, undervoltage

lockout, and thermal shutdown.

CONTROL SCHEME

The ADP2360 uses a single-pulse, peak current PFM control

scheme. A switching cycle is started when the FB pin voltage,

on. While the PMOS is on, the current through the inductor

in the inductor. The current through the inductor continues to

the PMOS turns off.

When the PMOS turns off, the NMOS turns on, reducing the

energy stored in the inductor until the inductor current reaches

zero. At this point, the NMOS also turns off.

When both the NMOS and PMOS are off, the ADP2360 enters

into sleep mode. During this phase of operation, the stored energy

switching cycle begins.

PMOS

NMOS

Figure 22. Control Scheme Typical Waveforms