ADP2360ACPZ-5.0-R7 datasheet(12/16 Pages) AD

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Data Sheet

ADP2360

Rev. 0 | Page 11 of 15

100% Duty Cycle

Because the PMOS turns off only if the peak current is reached or

if the feedback voltage exceeds VFB_RISING, the ADP2360 seamlessly

operates up to 100% duty cycle. This situation arises when the

input and output voltage are nearly equal. If the input voltage drops

below the output voltage, the output is maintained with a small

voltage drop across the PMOS device. When operating in 100%

duty cycle, the output current limit is approximately equal to IPEAK.

Steps must be taken to ensure that the load does not exceed 50% of

IPEAK to avoid the current limit when the input voltage rises above

the output voltage.

Adjustable Peak Current Threshold (ITH)

The control method of the ADP2360 means that the maximum

output current is slightly less than half of IPEAK. This peak current

value is resistor programmable with RITH.

The IPEAK value set by RITH on the ITH pin is determined at

startup and is reset only if the device is disabled and reenabled

using the EN pin or a VIN power cycle.

DEVICE FEATURES

Fixed and Adjustable Output Models

Both fixed and adjustable output models are available. The fixed

output models provide the feedback resistors internally.

Shutdown/Precision Enable

The EN pin of the ADP2360 tolerates the full supply voltage range

and provides three states of operation for the device: shutdown,

sleep, and active. When the EN pin voltage (VEN) is less than

VEN_SHUTDOWN, the ADP2360 is in shutdown mode and the VIN

supply current is at the lowest value (IQ_SHUTDOWN).

When VEN rises above VEN_SHUTDOWN but is below VEN_RISING, some

internal circuitry is enabled and the device is in standby mode.

This circuitry enables the references that provide the precision

enable threshold.

The precision enable turns on the regulator when the EN pin

voltage rises above VEN_RISING and returns to standby mode when

the voltage falls below VEN_RISING − VEN_HYS.

Soft Start

When the ADP2360 is enabled, an internal current source supplies

current (ISS) to the soft start capacitor (CSS) until it reaches

approximately 1 V at startup. During this time, VSS replaces the

internal feedback reference for the feedback comparator. This

reference rises at the same rate as VSS to the 0.8 V regulation level.

After VSS reaches 0.8 V, the feedback voltage reference is switched to

an 0.8 V internal reference. When VSS reaches approximately 1 V,

the SS pin is connected to an internal pull-down resistor and

discharged to 0 V. See Figure 23 for a diagram showing the soft

start time period and the behavior of the SS pin.

tSS

VSS

0.8V

Figure 23. Soft Start Voltage Time Period

Calculate the soft start time using the following equation:





(1)

When the ADP2360 is disabled via the EN pin, a UVLO event,

or a TSD event, the SS pin is reset. When the device is enabled

or the condition causing the UVLO or TSD event is removed,

the full soft start sequence occurs.

Thermal Shutdown (TSD)

The ADP2360 includes an internal TSD protection circuit. If the

junction temperature exceeds TSHDN, the TSD disables switching

and reduces the power dissipation in the device. While in thermal

shutdown, the power PMOS and NMOS devices are turned off

and the soft start capacitor, CSS, is discharged to AGND. When

the junction temperature decreases to TSHDN – THYS, the ADP2360

initiates a soft start and resumes switching to regulate the

output voltage.

Undervoltage Lockout (UVLO)

The ADP2360 has an internal UVLO on the VIN pin. If the input

voltage is falls below the VUVLO_FALLING threshold, the ADP2360

is disabled. The ADP2360 does not resume operation until the

input voltage rises above the VUVLO_RISING threshold.

Power Good

The ADP2360 has an active high, internal, open-drain, 60 V,

NMOS device connected to the power-good pin (PG) that is

used as a flag to indicate the status of the output voltage. To

configure the PG output, connect a pull-up resistor from PG

to an external voltage rail. An internal current limit prevents

damage to this pin.

When the feedback pin voltage (VFB) is less than VPG_RISING, the

open-drain NMOS is on, and PG is pulled to ground. When the

internal feedback voltage exceeds VPG_RISING, the open-drain

NMOS turns off.

The PG pin has hysteresis to prevent glitching. The NMOS

remains off until the internal feedback voltage falls below the

VPG_FALLING threshold.

If EN is low or a TSD or UVLO event occurs, an internal discharge

resistor is internally connected from the SW node to PGND. This

resistor pulls the output voltage to ground when the regulator is

disabled, even when there is no load on the output.

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