ADP2360

Data Sheet

Rev. 0 | Page 14 of 15

PCB LAYOUT CONSIDERATIONS

For high efficiency, good regulation, and stability with the

ADP2360, a well designed PCB is required. Poor layout can

affect the ADP2360 buck performance, causing electromagnetic

interference (EMI), poor electromagnetic compatibility (EMC),

ground bounce, and voltage losses.

Use the following guidelines when designing PCBs:



and the inductor, L1, as close as possible to the ADP2360.

Avoid long trace lengths from the device to the capacitors

that add series inductance and may cause EMI issues or

increased ripple.





Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.



Keep high current traces as short and as wide as possible.



Avoid routing high impedance traces near any node

connected to SW or near the inductor to prevent radiated

noise injection.



Use a ground plane with several vias connected to the

component side ground to reduce noise interference on

sensitive circuit nodes.



Be aware that traces may carry up to 60 V and leave

adequate separation between traces where necessary.



Because up to 60 V may be present between the EPAD and

device pins, the EPAD must be solder mask defined and

reduced slightly in size to prevent the risk of bridging if the

device is misaligned. To help ensure alignment during

reflow processes, traces must exit the pads perpendicular to

the device edge as shown in Figure 26. See the AN-772

Application Note, A Design and Manufacturing Guide for

the Lead Frame Chip Scale Package (LFCSP), for further

guidance on layout, footprint, and manufacturing.

Figure 26. PCB Layout, Top

Figure 27. PCB Layout, Bottom