P9027LP-R Datasheet

© 2016 Integrated Device Technology, Inc

19

April 28, 2016

The intent of this register is to identify the device is P9027LP-R.

Table 11. Device Identification

Byte

Address

Byte Name

Bit

Field Typical

Default

Value

Description

0xFC

Part_number_H

7:0

R/W

0x90

High byte of part number

0xFD

Part_number_L

7:0

R/W

0x27

Low byte of device naming code

This register will provides information about firmware version programmed into the IC.

Table 12. Firmware Version ID

Byte

Address

Byte Name

Bit

Field Typical

Default

Value

Description

0xFF

CHIP_ID_L

7:0

R

0xAB

Firmware version

All the faults can cause P9027LP-R send EPT (End of Power Transfer) package with different values or pull INT pin high. The faults can be

enabled by setting Masked Fault Enable Register. Bit of FLT_RAW will be set if corresponding fault condition is trigged.

Table 13. Masked Fault Enable Register

Byte

Address Byte Name

Bit

Field Typical

Default

Value

Description

0xD4

FLT_RAW_15

7

R

0

Reserved.

0xD4

FLT_RAW_14

6

R

0

Reserved.

0xD4

FLT_RAW_13

5

R

0

Reserved

0xD4

FLT_RAW_12

4

R

0

Reserved.

0xD4

FLT_RAW_11

3

R

0

Reserved

0xD4

FLT_RAW_10

2

R

0

Reserved.

0xD4

FLT_RAW_9

1

R

0

Reserved

0xD4

FLT_RAW_8

0

R

0

Reserved

0xD5

FLT_RAW_7

7

R

0

TS2 voltage is above programmed voltage.

0xD5

FLT_RAW_6

6

R

0

TS1 voltage is above programmed voltage.

0xD5

FLT_RAW_5

5

R

0

“1” when die temperature is greater than Tdie_shutdown.

0xD5

FLT_RAW_4

4

R

0

Reserved

0xD5

FLT_RAW_3

3

R

0

Reserved