P9242-R Datasheet

© 2016 Integrated Device Technology, Inc

10

December 16, 2016

Symbol

Description

Conditions/Notes

Min

Typical

Max

Units

LDO18[b]

1.8V LDO Regulator

1.71

1.8

1.89

V

LDO33[b]

3.3V LDO Regulator

3.15

3.3

3.45

V

PREG

5V LDO Regulator

5

V

Thermal Shutdown

Thermal Shutdown

Threshold rising

140

°

C

Threshold falling

120

°

C

Analog Input Pins Input Current Leakage (TS, VCOIL)

Leakage Current

-1

1

µA

Open-Drain Pins Output Logic Levels (LED1, LED2, SCL, SDA)

Output Logic HIGH

4

V

Output Logic LOW

I = 8mA

0.5

V

Digital Input/Output Pins Logic Levels

Input Voltage HIGH Level

0.7

VDDIO

V

Input Voltage LOW Level

0.3

VDDIO

V

Leakage Current

1

µA

Output Logic HIGH

I = 8mA, VDDIO = 3.3V

2.4

V

Output Logic LOW

I = 8mA, VDDIO = 3.3V

0.5

V

Clock Frequency

400

kHz

Capacitive Load

For each bus line

100

pF

SCL, SDA Input Capacitance

5

pF

Input Leakage Current

V = GND and 3.3V

-1

1

µA

[a] The input voltage operating range is dependent upon the type of transmitter power stage (full-bridge, half-bridge) and transmitting coil inductance.

WPC specifications should be consulted for appropriate input voltage ranges by end-product type.

[b] Do not externally load. For internal biasing only.

[c] A 20mΩ, 1% or better sense resistor and a 4.7Ω, 1% input filter resistor are required to meet the FOD specification.