ZLED7025 datasheet(18/26 Pages) IDT

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ZSLS7025 Datasheet

April 20, 2016

4.2.3

High Frequency Noise Filter Capacitor CVDD

External capacitor CVDD forms a high-frequency noise filter for the VDD pin. For all configurations, use CVDD to bypass

the VDD pin using a low ESR capacitor (a 10µF ceramic capacitor is recommended) to provide a high frequency path

to GND.

4.2.4

Input Capacitor CIN

The CIN input capacitor connected to VIN will supply the transient input current for the power inductor. A value of

100μF or higher is recommended to prevent excessive input voltage ripple. Also see section 4.2.3.

4.2.5

Output Capacitor COUT for Reducing Output Ripple

The output capacitor (COUT) holds the output current while the Q1 external MOSFET turns ON. This capacitor directly

impacts the line regulation and the load regulation.

Using a low ESR capacitor can minimize output ripple voltage and improve output current regulation. For most

applications, a 220μF low ESR capacitor will be sufficient. Proportionally lower ripple can be achieved with higher

capacitor values.

4.2.6

Schottky Rectifier Diode D1

The D1 external diode for the ZSLS7025 should be a Schottky diode with a low forward voltage drop and fast

switching speed. The diode’s average current rating must exceed the application’s average output current. The

diode’s maximum reverse voltage rating must exceed the over-voltage protection of the application. For PWM

dimming applications, note the reverse leakage of the Schottky diode. Lower leakage current will drain the output

capacitor less during PWM low periods, allowing for higher PWM dimming ratios.

4.2.7

External MOSFET Q1

The Q1 external MOSFET must have a VDS rating that exceeds the maximum over-voltage protection (OVP) level

configured for the application. The VGS(th) of the MOSFET should be not higher than 4V. The MOSFET’s current rating

must be higher than the input peak current (IIN_PEAK). Determine the power dissipation within Q1 and check if the

thermal resistance of the MOSFET package causes the junction temperature to exceed maximum ratings. Also see

section 2.10 regarding the effect of the MOSFET RDS(ON) on DC power loss.

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