ZSLS7031 Datasheet

© 2016 Integrated Device Technology, Inc.

18

January 26, 2016

4

ESD Protection

All pins have an ESD protection of

≥ ±2000V according to the Human Body Model (HBM). The ESD test follows

the Human Body Model based on MIL 883-H, Method 3015.8.

5

Pin Configuration and Package

Figure 5.1

ZSLS7031 Pin Assignments Top View

Table 5.1

Pin Description MSOP-8

FB

CS

GATE

VCC

GND

FSET

n.c.

VSINE

1

2

3

4

6

5

7

8

Pin Name

NO.

Description

VSINE

1

Line voltage sense input required for PFC.

NC

2

Not connected. Leave floating in the application.

FSET

3

Connect a resistor from this pin to GND to set the operating frequency.

GND

4

Ground. Common potential to all internal circuitry.

FB

5

Auxiliary winding voltage sensing pin for OVP.

CS

6

Primary winding peak current sensing input.

GATE

7

External power NMOS gate driving output.

VCC

8

Internal circuit power supply input.