WM8955L datasheet(35/43 Pages) WOLFSON

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WM8955L

Product Preview Rev 0.4 May2003

POWER SUPPLIES

The WM8955L can use up to four separate power supplies:

•

AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers.

AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power

consumption (except for power consumed in the headphone). A large AVDD slightlyimproves

audio quality.

•

HPVDD / HPGND: Headphone supply, powers the headphone drivers. HPVDD can range from

1.8V to 3.6V. HPVDD is normallytied to AVDD, but it requires separate layout and decoupling

capacitors to curb harmonic distortion. With a larger HPVDD, louder headphone outputs can be

achieved with lower distortion. If HPVDD is lower than AVDD, the output signal maybe clipped.

•

DCVDD: Digital core supply, powers all digital functions except the audio and control

interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The

return path for DCVDD is DGND, which is shared with DBVDD.

•

DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it

possible to run the digital core at verylow voltages, saving power, while interfacing to other

digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has

no effect on audio quality. The return path for DBVDD is DGND, which is shared with DCVDD.

It is possible to use the same supplyvoltage on all four. However, digital and analogue supplies

should be routed and decoupled separatelyto keep digital switching noise out of the analogue signal

paths.

POWER MANAGEMENT

The WM8955L has two control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To avoid anypop or click noise,

it is important to enable or disable functions in the correct order (see Applications Information)

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

VMID resistor divider select

00 – VMID disabled

01 – 50k

Ω divider enabled

10 – 500k

Ω divider enabled

R25 (19h)

Power

Management

(1)

VREF

VREF (necessaryfor all other functions)

DACL

DAC Left

DACR

DAC Right

LOUT1

LOUT1 Output Buffer*

ROUT1

ROUT1 Output Buffer*

LOUT2

LOUT2 Output Buffer*

ROUT2

ROUT2 Output Buffer*

MOUT

MONOOUT Output Buffer and Mono Mixer

R26 (1Ah)

Power

Management

(2)

OUT3

OUT3 Output Buffer

Note: All control bits are 0=OFF, 1=ON

* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when

ROUT1=1 or ROUT2=1.

Table 26 Power Management

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