WM8955L datasheet(36/43 Pages) WOLFSON

36 / 43 page

WM8955L

Product Preview

Product Preview Rev 0.4 May2003

STOPPING THE MASTER CLOCK

In order to minimise power consumed in the digital core of the WM8955L, the master clock should be

stopped in Standbyand OFF modes. If this is cannot be done externallyat the clock source, the

DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core.

However, since setting DIGENB has no effect on the power consumption of other system

components external to the WM8955L, it is preferable to disable the master clock at its source

wherever possible.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Additional Control

(1)

DIGENB

Master clock disable

0: master clock enabled

1: master clock disabled

Table 2 ADC andDAC Oversampling Rate Selection

NOTE: Before DIGENB can be set, the control bits DACL andDACR must be set to zero anda

waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs

andADCs from re-starting correctly.

OVERSAMPLING RATE

Bydefault, the oversampling rate of the DAC digital filters is 128x. However, this can be changed to

64x bywriting to the DACOSR bit. In the 64x oversampling mode, the digital filters consumes less

power. However, the signal-to-noise ratio is slightlyreduced.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DACOSR

DAC oversample rate select

1 = 64x (lowest power)

0 = 128x (best SNR)

Table 27 Oversampling Rate Selection

SAVING POWER AT LOW SUPPLY VOLTAGES

The analogue supplies to the WM8955L can run from 1.8V to 3.6V. Bydefault, all analogue circuitry

on the device is optimized to run at 3.3V. This set-up is also good for all other supplyvoltages down

to 1.8V. However, at lower voltages, it is possible to save power byreducing the internal bias

currents used in the analogue circuitry. This is controlled as shown below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R23 (17h)

Additional

Control(1)

7:6

VSEL[1:0]

Analogue Bias optimization

00 : Lowest bias current, optimized for 1.8V

01 : Low bias current, optimized for 2.5V

10, 11 : Default bias current, optimized for 3.3V

Table 28 Analogue Bias Selection

WM8955L 数据表(PDF) 36 Page - Wolfson Microelectronics plc

WM8955L 数据表(HTML) 36 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载

链接网址

WM8955L 数据表(PDF) 36 Page - Wolfson Microelectronics plc

WM8955L 数据表(HTML) 36 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表 下载

链接网址

数据表下载