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MAX96708 数据表(PDF) 27 Page - Maxim Integrated Products

部件名 MAX96708
功能描述  14-Bit GMSL Deserializer
PDF  68 Pages
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制造商  MAXIM [Maxim Integrated Products]
网页  https://www.maximintegrated.com/en.html
标志 MAXIM - Maxim Integrated Products

MAX96708 数据表(HTML) 27 Page - Maxim Integrated Products

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Bus Widths
The serial link has multiple bus-width settings that
determine the parallel bus width and the resulting parallel
word rate. The serial link operates to a maximum serial
bit rate of 1.74Gbps. The BWS bit determines if each
serial packet is 30 or 40 bits long, which translates to a
maximum serial packet rate; thus, a maximum parallel
word rate of 58MHz or 43.5MHz when BWS = 0 or 1,
respectively. Decoding translates the 30- or 40-bit serial
packets into 24, or 32 parallel bits. One bit is used for
parity, while a second is reserved for the control channel.
An additional 6 bits is used during optional 6-bit CRC. In
addition, double mode splits the remaining word size in
half if used. The remaining bits can be used for video bits
minus any sync bits if HV encoding is not used.
Note: The following modes list the internal bus widths.
The number of available input and output pins may limit
the actual bus width available.
24-Bit Mode (Figure 14)
When BWS = 0, the 30-bit serial packet corresponds with
three 8b/10b symbols, representing 24 bits (24-bit mode).
After parity and control channel, this leaves 16/22 bits of
video data if CRC is/is not used (single mode), or 8/11 bits
of video data if CRC is/is not used (double mode).
Figure 14. 24-Bit Mode Serial-Data Format
24-BIT
MODE
PACKET PARITY-
CHECK BIT
FCC
PCB
D0
D1
D21
D20
D19
D18
D17
SERIAL
DATA
NO PXL_CRC
RX/
SDA
TX/
SCL
UART/I2C
FORWARD CONTROL-
CHANNEL BIT
D0
D1
D21
D0
D1
D15
D21
D20
D19
D18
D17
2 BITS
16 VIDEO
BITS
D16
D15
22 BITS
22 VIDEO
BITS
D16
6
PXL_CRC
BITS
PXL_CRC ON
PXL_CRC
DBL = 0
D0
D1
D21
22 VIDEO
BITS*
DBL = 1
D0
D1
D10
D11
D12
D21
11 x 2
VIDEO
BITS*
D0
D1
D15
16 VIDEO
BITS*
D0
D1
D7
D8
D9
D15
8 x 2
VIDEO
BITS*
DBL = 0
DBL = 1
NO PXL_CRC, DBL = 0
58MHz MAX
NO PXL_CRC, DBL = 1
116MHz MAX
PXL_CRC ON, DBL = 0
58MHz MAX
PXL_CRC ON, DBL = 1
116MHz MAX
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
www.maximintegrated.com
Maxim Integrated │ 27
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input



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