Electrical Characteristics

DIGITAL DC CHARACTERISTICSUnless otherwise noted, these specifications apply for +V

Boldface limits apply for T

Symbol

Parameter

Conditions

Typical

(Note 7)

Limits

(Note 8)

Units

(Limit)

V

IN(1)

SDA and SCL Logical “1” Input

Voltage

+V

V (min)

+V

V (max)

V

IN(0)

SDA and SCL Logical “0” Input

Voltage

−0.3

V (min)

+V

V (max)

V

IN(HYST)

SDA and SCL Digital Input

Hysteresis

500

250

mV (min)

V

IN(1)

A0 and A1 Logical “1” Input

Voltage

2.0

V (min)

+V

V (max)

V

IN(0)

A0 and A1 Logical “0” Input

Voltage

−0.3

V (min)

0.7

V (max)

I

IN(1)

Logical “1” Input Current

V

0.005

1.0

µA (max)

I

IN(0)

Logical “0” Input Current

V

−0.005

−1.0

µA (max)

C

IN

Capacitance of All Digital Inputs

20

pF

I

OH

High Level Output Current

V

10

µA (max)

V

OL

Low Level Output Voltage

I

0.4

V (max)

T_CRIT_A Output Saturation

Voltage

I

(Note 14)

0.8

V (max)

T_CRIT_A Delay

1

Conversions

(max)

t

OF

Output Fall Time

C

250

ns (max)

I

SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for +V

to +5.5V for LM92CIM . Boldface limits apply for T

noted. CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface limits apply for T

T

The switching characteristics of the LM92 fully meet or exceed the published specifications of the I

rameters are the timing relationship between SCL and SDA signal related to the LM92. They are not the I

tions.

Symbol

Parameter

Conditions

Typical

(Note 7)

Limits

(Note 8)

Units

(Limit)

t

1

SCL (Clock) Period

2.5

µs(min)

1

ms(max)

t

2

Data in Set-Up Time to SCL High

100

ns(min)

t

3

Data Out Stable after SCL Low

0

ns(min)

t

4

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns(min)

t

5

SDA High Hold Time after SCL High (Stop Condition)

100

ns(min)

t

TIMEOUT

SDA and SCL Time Low for Reset of Serial Interface

(Note 17)

75

300

ms (min)

ms

(max)

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