ADP3500

REV.PrP 2/6/02

- 19 -

200

nS

CLK set-up time

400

nS

CS set-up time

400

nS

CLK “High” Duration

400

nS

CLK “Low” Duration

500

nS

CS hold time

62

µS

CS recovery time

200

nS

Input data set-up time

200

nS

Input data hold time

300

nS

Data output delay time

300

nS

Data output floating time

300

nS

Data output floating time after CS goes low.

2.2.1. Function block

ADP3500 integrates the serial bus interface for easy communication with the system. The data bus consists of three wires,

CLK, CS, and DATA, and is capable of Serial to Parallel / Parallel to Serial conversion of data, as well as clock transfer.

Serial To Parallel

Conversion

Parallel to Serial

Conversion

Creation of

write Data

sp_data [7:0]

write_enable

sp_addr [5:0]

ps_data [7:0]

Synchlonization

and Data Selection

DATA

RW_SEL

resetin_n

CS

CLKIN

DATAIN

Figure 10. Serial Interface block diagram

Serial interface block works during the time period at CS signal enable. After the falling edge of CLKIN signal right after the

rising edge of CS signal, Address, transfer control signal and write data are held in sequentially. In case DATA READ, each of

data will be prepared by rising edge of CLKIN and baseband chip may want to read or latch the data at falling edge of CLKIN.

While CS is not asserted, CLKIN is ignored. If CS goes “L” while CLKIN is continuously applied or input DATA, all data is

canceled and DATA line would be High impedance. In this case, user needs to input the data again. Please note that CLKIN

should be stayed “L” when CS goes H. RTC counter registers should be accessed at a certain time (>62

µS) later after CS

assertion. Asserting RESETIN_N (RESETIN-) signal resets the block..

Notes:

•

CLKIN=10KHz to 1MHz, 20/80% duty cycle.

•

CLKIN should be “L” when CS goes “H”.

•

In case of RTC counter access, the access should be approximately 62

µS, (2 clock cycles of CLK32K) after the CS signal

is asserted, to hold the RTC value.

•

The CS should not be asserted for 62

µS, (2 clock cycles of CLK32K) after the CS is released.

•

CS signal should never be asserted for 1 sec or longer, otherwise RTC counter makes error.

2.2.2 Data input/output timing

Address(6bit)

R/W(2bit)

Read DATA(8bit)

4

3

2

1

0

5

1

0

7

6

5

4

3

2

1

0

PRELIMINARY TECHNICAL DATA