ADP3500

REV.PrP 2/6/02

- 17 -

CS

CLKIN

DATA

KEYPADROW

KEYPADCOL

GPIO[3:0]

RESETIN_N

32K OSC

OSCIN

OSCOUT

RSTDELAY_N

RESETOUT_N

RESET

PWRONKEY_N

OPT2_N

OPT3

chager_detect

voltage_detect

rtc_clk32k

INT_N

DELAY

10mS

keypad_int

TEST

4

4

6

clk32k

voltage detect_delay

power_on

TCXO_ON

test_mode

[VBAT]

write_data[7:0]

write_enable

sp_addr[4:0]

clk512

SLEEP_N

test_ldoenable

BLIGHT

DGND

batid

Analog

Blocks

LDO control register

pwronkey_n_sync,

opt1_n_sync,

opt3_sync

Interrupt

register

block

LED control

Analog block

KEY PAD

I/F

BL

GPIO

OPT1_N

Serial

I/F

Data

select

resetin_n

(reset for registers)

rtc_resetin_n

analog block

LDO

Control

32K CLK

output

control

32K OUT

RTC register block

clk1k

rtc_voltage_detect

rtc_voltage_detect

[RTCV]

reset output

control

SYNC.

RTC

Output data

select

Address

decode

Test mode

register

block

Stay-Alive

Timer

DATA

IN

POWER

OFF

INT

control

register

(reset & mask)

KEY PAD

I/F control

GPIO

control

Analog

control

registers

rtc_test

SYNC.

SYNC.

Figure 8. LOGIC block diagram

2.1 RESET

2.1.1 RESETIN- signal

The internal reset function is activated by external reset input, RESETIN-, and this is an asynchronous signal. The internal

reset signal is used in the following blocks.

• Serial I/F

• Interrupt control

• Stay-Alive timer

• Registers (refer to the Register section for detail).

LDOs, controlled by Serial I/F, are applied “RESET” by RESETIN-. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, LDO11

and REF0 are set to “0”. In case RESETIN- has noise, the internal circuit may be in reset and cause the system unexpected

result. Please take enough treatment. RESETIN- is level translated from LDO1 to both VBAT and RTCV supplies.

PRELIMINARY TECHNICAL DATA