ADP3500

REV.PrP 2/6/02

- 21 -

2.6 POWER ON INPUT

PWRONKEY and OPT1 have pull-up resistors, and others are not. In addition to these inputs, other internal input signals such

as charger_detect and Alarm signal (alarm_int) from RTC enable Main and Sub LDOs of LDO1, 2, 3 and LDO6. Power ON

status is hold by a latch data in Delay circuit, called voltage_detect_delay (please see 4.8 for more detail). OPT3 has a lower

voltage threshold. OPT2 is different structure to the other inputs, and is pulled down to zero by internal signal when phone is

Power ON status, in order to make sure to have Power ON status even if short-term disconnection is happened. Following is a

block diagram and Power on sequence.

VBAT

voltage_detect_delay

charger_detect

alarm_int

power_on

PWRONKEY-

OPT1-

OPT2-

OPT3

140K

Ω

140K

Ω

INT

Block

Figure 13. Power ON input block diagram

•

Voltage_detect_delay

: Voltage Detect Signal (10mS delay)

(1: Assert)

•

charger_detect

: Charger Detect Signal

(1: Assert)

•

alarm_int

: Alarm Detect Signal (Alarm 1 or 2)

(1: Assert)

•

PWRONKEY-

: Power On key input

(0: Assert)

•

OPT1-

: Power On signal

(0: Assert)

•

OPT2-

: Power On signal

(0: Assert)

•

OPT3

: Power On signal

(1: Assert)

PRELIMINARY TECHNICAL DATA