Philips Semiconductors

Product data sheet

PCA9512

2004 Oct 05

6

Resistor Pull-up Value Selection

The system pull-up resistors must be strong enough to provide a

positive slew rate of 1.25 V/

µs on the SDA and SCL pins, in order to

activate the boost pull-up currents during rising edges. Choose

maximum resistor value using the formula:

R

picofarads (pF).

In addition, regardless of the bus capacitance, always choose

R

maximum. The start-up circuitry requires logic HIGH voltages on

SDAOUT and SCLOUT to connect the backplane to the card, and

these pull-up values are needed to overcome the precharge voltage.

See the curves in Figures 5 and 6 for guidance in resistor pull-up

selection.

30

20

15

21

5

0

0

100

200

300

400

(k

Ω)

25

RECOMMENDED

PULL-UP

RISE-TIME > 300 ns

SW02115

Figure 5. Bus requirements for 3.3 V systems

20

15

21

5

0

0

100

200

300

400

(k

Ω)

RECOMMENDED

PULL-UP

RISE-TIME

> 300 ns

SW02116

Figure 6. Bus requirements for 5 V systems

Minimum SDA and SCL Capacitance

Requirements

The device connection circuitry requires a minimum capacitance

loading on the SDA and SCL pins in order to function properly. The

resistance. Estimate the bus capacitance on both the backplane and

the card data and clock buses, and refer to Figures 5 and 6 to

choose appropriate pull-up resistor values. Note from the figures

that 5 V systems should have at least 47 pF capacitance on their

buses and 3.3 V systems should have at least 22 pF capacitance for

proper operation of the PCA9512. Although the device has been

designed to be marginally stable with smaller capacitance loads, for

applications with less capacitance, provisions need to be made to

add a capacitor to ground to ensure these minimum capacitance

conditions if oscillations are noticed during initial signal integrity

verification.