PCA9512DP datasheet(10/16 Pages) PHILIPS

10 / 16 page

Philips Semiconductors

Product data sheet

PCA9512

Level shifting hot swappable I2C and SMBus buffer

2004 Oct 05

ELECTRICAL CHARACTERISTICS

VCC = 2.7 V to 5.5 V; Tamb = –40 °C to +85 °C unless otherwise noted.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Power supply

VCC

Supply voltage

Note 1.

2.7

—

5.5

VCC2

Card side supply voltage

Note 1.

2.7

—

5.5

IVCCI

VCC supply current

VCC = 5.5 V; VSDAIN = VSCLIN = 0 V

—

1.2

3.6

IVCC2

VCC supply current

VCC = 5.5 V; VSDAOUT = VSCLOUT = 0 V

—

1.1

2.4

Start-up circuitry

VPRE

Precharge voltage

SDA, SCL floating; Note 1.

0.8

1.1

1.2

tEN

Enable time on power-up

Note 6.

—

180

—

µs

tIDLE

Bus idle time

Notes 1 and 7.

140

250

µs

Rise time accelerators

IPULLUPAC

Transient boosted pull-up current

Positive transition on SDA, SCL,

ACC = 0.7 V

× VCC2; VCC = 2.7 V;

Slew rate = 1.25 V/

µs; Note 2.

—

VACCDIS

Accelerator disable threshold

0.3

× VCC2

0.5

× VCC2

—

VACCEN

Accelerator enable threshold

—

0.5

× VCC2 0.7 × VCC2

IVACC

ACC input current

–1

± 0.1

µA

tPDOFF

ACC delay, on/off

—

Input–output connection

VOS

Input–output offset voltage

10 k

Ω to VCC on SDA, SCL;

VCC = 3.3 V, VCC2 = 3.3 V;

VIN = 0.2 V; Note 1; Note 3.

150

fSCL_SDA

operating frequency

Guaranteed by design, not subject to

test

—

400

kHz

CIN

Digital input capacitance

Guaranteed by design,

not subject to test

—

VOL

LOW-level output voltage

Input = 0 V. SDA, SCL pins;

ISINK = 3 mA; VCC = 2.7 V;

VCC2 = 2.7 V; Note 1.

—

0.4

ILI

Input leakage current

SDA, SCL pins = VCC = 5.5 V;

VCC2 = 5.5 V

–1

—

µA

Timing characteristics

fI2C

I2C operating frequency

Note 4

—

400

kHz

tBUF

Bus free time between stop and

start condition

Note 4

1.3

—

µs

tHD;STA

Hold time after (repeated) start

condition

Note 4

0.6

—

µs

tSU;STA

Repeated start condition setup

time

Note 4

0.6

—

µs

tSU;STO

Stop condition setup time

Note 4

0.6

—

µs

tHD;DAT

Data hold time

Note 4

300

—

tSU;DAT

Data setup time

Note 4

100

—

tLOW

Clock LOW period

Note 4

1.3

—

µs

tHIGH

Clock HIGH period

Note 4

0.6

—

µs

Clock, data fall time

Notes 4 and 5

20 + 0.1

× CB

—

300

Clock, data rise time

Notes 4 and 5

20 + 0.1

× CB

—

300

NOTES:

1. This specification applies over the full operating temperature range.

2. IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section.

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