PCA9512DP datasheet(2/16 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

PCA9512

Level shifting hot swappable I2C and SMBus buffer

2004 Oct 05

DESCRIPTION

The PCA9512 is a hot swappable I2C and SMBus buffer that allows

I/O card insertion into a live backplane without corruption of the data

and clock buses and includes two dedicated supply voltage pins to

provide level shifting between 3.3 V and 5 V systems while

maintaining the best noise margin for each voltage level. Either pin

may be powered with supply voltages ranging from 2.7 V to 5.5 V

with no constraints on which supply voltage is higher. Control

circuitry prevents the backplane from being connected to the card

until a stop bit or bus idle occurs on the backplane without bus

contention on the card. When the connection is made, the PCA9512

provides bi-directional buffering, keeping the backplane and card

capacitances isolated.

The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers

allow them to be connected to another PCA9510/11/12/13/14 device

in series or in parallel and to the A side of the PCA9517. The

PCA9510/11/12/13/14 can not connect to the static offset I/Os used

on the PCA9515/15A/16/16A/17 B side and PCA9518.

FEATURES

• Bi-directional buffer for SDA and SCL lines increases fanout and

prevents SDA and SCL corruption during live board insertion and

removal from multi-point backplane systems

• Compatible with I2C standard mode, I2C fast mode, and SMBus

standards

• ∆V/∆t rise time accelerators on all SDA and SCL lines with ability

to disable

∆V/∆t rise time accelerators through the ACC pin for

lightly loaded systems

• 5 V to 3.3 V level translation with optimum noise margin

• High-impedance SDA, SCL pins for V

CC or VCC2 = 0 V

• 1 V precharge on all SDA and SCL lines

• Supports clock stretching and multiple master

arbitration/synchronization

• Operating power supply voltage range: 2.7 V to 5.5 V

• 5.5 V tolerant I/Os

• 0 kHz to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Packages offered: SO8, TSSOP8 (MSOP8)

APPLICATION

• cPCI, VME, AdvancedTCA cards and other multi-point backplane

cards that are required to be inserted or removed from an

operating system.

PIN CONFIGURATION

VCC2

GND

SCLIN

SDAOUT

SDAIN

ACC

VCC

SCLOUT

SW02070

TOP VIEW

Figure 1. Pin configuration.

PIN DESCRIPTION

SYMBOL

DESCRIPTION

VCC2

Supply voltage for devices on the card

I2C-buses. Connect pull-up resistors from

SDAOUT and SCLOUT to this pin.

SCLOUT

Serial clock output to and from the SCL bus

on the card.

SCLIN

Serial clock input to and from the SCL bus

on the backplane.

GND

Ground. Connect this pin to a ground plane

for best results.

ACC

CMOS threshold digital input pin that

enables and disables the rise-time

accelerators on all four SDA and SCL pins.

ACC enables all accelerators when set to

VCC2, and turns them off when set to GND.

SDAIN

Serial data input to and from the SDA bus on

the backplane/long distance bus.

SDAOUT

Serial data output to and from the SDA bus

on the card.

VCC

Power supply. From the backplane, connect

pull-up resistors from SDAIN and SCLIN to

this pin.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

8-pin plastic SO

–40

°C to +85 °C

PCA9512D

PCA9512

SOT96-1

8-pin plastic TSSOP (MSOP)

–40

°C to +85 °C

PCA9512DP

9512

SOT505-1

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.

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