THCV231_THCV236_Rev.2.30_E

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THine Electronics, Inc.

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Security E

Table 32. Sub-Link Slave Control Register

Address

(Hex)

Bit#

R/W

Default

(Hex)

Name

Description

Note

0x80

7:0

R

0x00

Reserved

-

0x81

7:1

R

0x00

Reserved

-

0

RW

0

2WIRE_RST

2-wire serial I/F reset

Write 1: 16 pulse SCL signal is sent to 2-wire serial slave device

connected to Sub-Link Slave.

This bit is a remedy against SDA=L, 2-wire serial stuck condition.

Automatically cleared into 0 after reset action.0 is always read.

-

0x82

7:6

R

0x0

Reserved

5

RW

0

2WIRE_RST_END_INT

Cause of interrupt 2-wire serial reset done

0: Normal operation

1: 2-wire serial reset signal has all finished

Any write action: clear this bit into 0

-

4

RW

0

2WIRE_NACK_INT

Cause of interrupt 2-wire serial Slave NACK

0: No NACK from remote side 2-wire serial slave ever

1: NACK from remote side 2-wire serial slave once come

Any write action: clear this bit into 0

-

3

R

0

GPIO_INT

Cause of interrupt Sub-Link Slave GPIO

0: No change in Slave GPIO inputs ever

1: Slave GPIO inputs have once changed.

This bit is cleared when GPIOn_INPUT_MONITOR (n=4,3) register

(0xC1) is read.

-

2

RW

0

COMERR_INT

Cause of interrupt Sub-Link communication Error

0: No communication error on Sub-Link ever

1: Communication error on Sub-Link once happened

Any write action: clear this bit into 0

-

1

RW

0

2WIRE_TIMEOUT_INT

Cause of interrupt 2-wire serial time out

0: 2-wire serial access in time ever

1: 2-wire serial access has once had time out

Any write action: clear this bit into 0

-

0

RW

0

SLINK_TIMEOUT_INT

Cause of interrupt Sub-Link time out0: Sub-Link access in time ever

1: Sub-Link has once had time out

Any write action: clear this bit into 0

-

0x83

7:6

R

0x0

Reserved

-

5

RW

0

2WIRE_RST_ENABLED_INT_ENABLE

0: "2WIRE_RST_END_INT" is blocked to be reported to Master Side.

1: "2WIRE_RST_END_INT" is allowed to be reported to Master Side.

(*1)

4

RW

0

2WIRE_NACK_INT_ENABLE

0: "2WIRE_NACK_INT" is blocked to be reported to Master Side.

1: "2WIRE_NACK_INT" is allowed to be reported to Master Side.

3

RW

0

GPIO_INT_ENABLE

0: "GPIO_INT" is blocked to be reported to Master Side.

1: "GPIO_INT" is allowed to be reported to Master Side.

2

RW

0

COMERR_INT_ENABLE

0: "COMERR_INT" is blocked to be reported to Master Side.

1: "COMERR_INT" is allowed to be reported to Master Side.

1

RW

0

2WIRE_TIMEOUT_INT_ENABLE

0: "2WIRE_TIMEOUT_INT" is blocked to be reported to Master Side.

1: "2WIRE_TIMEOUT_INT" is allowed to be reported to Master Side.

0

RW

0

SLINK_TIMEOUT_INT_ENABLE

0: "SLINK_TIMEOUT_INT" is blocked to be reported to Master Side.

1: "SLINK_TIMEOUT_INT" is allowed to be reported to Master Side.

0x84

-0x8B

7:0

R

0x00

Reserved

-

0x8C

7

R

0

Reserved

-

6:0

RW

0x2D

SCL_W_H

-

0x8D

7

R

0

Reserved

-

6:0

RW

0x37

SCL_W_L

-

0x8E

7:2

R

0x00

Reserved

-

1:0

RW

0x0

Reserved. Must be 0

-

0x8F

7:2

R

0x00

Reserved

-

1:0

RW

0x1

Reserved

-

0x90

-0xBF

7:0

R

0x00

Reserved

-

*1

Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT).