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THCV231 数据表(PDF) 48 Page - THine Electronics, Inc. |
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THCV231 数据表(HTML) 48 Page - THine Electronics, Inc. |
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48 / 56 page ![]() THCV231_THCV236_Rev.2.30_E Copyright©2016 THine Electronics, Inc. THine Electronics, Inc. 48/56 Security E Lock and Unlock Sequence VDD CLKIN PDN Fix to CAPINA TXP/N D11-D0 HSYNC,VSYNC Training pattern Normal pattern Training pattern Data tTPD tTPLL0 tTNP1 tTNP0 tTPLL1 HTPDN LOCKN Register(0x00 bit0) on THCV236 Register(0x00 bit1) on THCV236 Data Figure 23. THCV231 Lock/Unlock Sequence RXP/N HTPDN PDN0 LOCKN CLKOUT Training pattern Normal pattern VDD Low tRPD tRHPD0 tRHPD1 tRPLL0 tRLCK0 tRPLL1 Low Low tRLCK1 Data D11-D0 HSYNC,VSYNC Register(0x00 bit0) Register(0x00 bit1) tROSC0 CLKOUT Low Low (OUTSEL=0) (OUTSEL=1) Low tROSC1 tROSC2 Permanent Clock (Internal OSC Clock) Pixel Clock Pixel Clock Permanent Clock (Internal OSC Clock) Valid Clock Invalid Clock Valid Clock tOSC/N (N=1,2,4,8)(*1) *1 N depends on setting of OUTSEL_SETTING register (0x6D bit1,0). See Register Map (Table 36) InValid Data Figure 24. THCV236 Lock/Unlock Sequence |
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