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MPC860DP 数据表(PDF) 38 Page - Motorola, Inc |
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MPC860DP 数据表(HTML) 38 Page - Motorola, Inc |
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38 / 76 page  38 MPC860 Family Hardware Specifications MOTOROLA Bus Signal Timing Figure 9-29 provides the input timing for the debug port clock. Figure 9-29. Debug Port Clock Input Timing Figure 9-30 provides the timing for the debug port. Figure 9-30. Debug Port Timings Table 9-10. Debug Port Timing Num Characteristic All Frequencies Unit Min Max P61 DSCK cycle time 3 × TCLOCKOUT —— P62 DSCK clock pulse width 1.25 × TCLOCKOUT —— P63 DSCK rise and fall times 0.00 3.00 ns P64 DSDI input data setup time 8.00 — ns P65 DSDI data hold time 5.00 — ns P66 DSCK low to DSDO data valid 0.00 15.00 ns P67 DSCK low to DSDO invalid 0.00 2.00 ns DSCK D61 D61 D63 D62 D62 D63 DSCK DSDI DSDO D64 D65 D66 D67 |
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