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AT89C51CC03U-RDTIM 数据表(PDF) 163 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 数据表(HTML) 163 Page - ATMEL Corporation |
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163 / 195 page  163 AT89C51CC03 4182I–CAN–06/05 Table 111. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Reset Value = xxxx 0000b bit addressable 76 543 210 - - - - ESPI ETIM EADC ECAN Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3 ESPI SPI Interrupt Enable bit Clear to disable the SPI interrupt. Set to enable the SPI interrupt. 2ETIM TImer Overrun Interrupt Enable bit Clear to disable the timer overrun interrupt. Set to enable the timer overrun interrupt. 1 EADC ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. 0ECAN CAN Interrupt Enable bit Clear to disable the CAN interrupt. Set to enable the CAN interrupt. |
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