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AT89C51CC03U-RDTIM 数据表(PDF) 165 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 数据表(HTML) 165 Page - ATMEL Corporation |
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165 / 195 page  165 AT89C51CC03 4182I–CAN–06/05 Table 113. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value = XXXX 0000b bit addressable 76 543 210 - - - - SPIL POVRL PADCL PCANL Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3 SPIL SPI Interrupt Priority Level Less Significant Bit Refer to SPIH for priority level. 2POVRL Timer Overrun Interrupt Priority Level Less Significant Bit Refer to PI2CH for priority level. 1PADCL ADC Interrupt Priority Level Less Significant Bit Refer to PSPIH for priority level. 0PCANL CAN Interrupt Priority Level Less Significant Bit Refer to PKBH for priority level. |
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