S2-LPQTR datasheet(76/90 Pages) STMICROELECTRONICS

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Table 59: Register contents

Name

Addr

Default

Bit

Field name

Description

GPIO0_CONF

7:3

GPIO_SELECT

Specify the GPIO0 I/O signal, default setting POR

(see Table 57).

RESERVED

1:0

GPIO_MODE

GPIO0 Mode:



01b: Digital Input



10b: Digital Output Low Power



11b: Digital Output High Power

GPIO1_CONF

7:3

GPIO_SELECT

Specify the GPIO1 I/O signal, default setting digital

GND (see Table 57).

RESERVED

1:0

GPIO_MODE

GPIO1 Mode:



01b: Digital Input1



0b: Digital Output Low Power



11b: Digital Output High Power

GPIO2_CONF

7:3

GPIO_SELECT

Specify the GPIO2 I/O signal, default setting digital

GND (see Table 57).

RESERVED

1:0

GPIO_MODE

GPIO2 Mode:



01b: Digital Input



10b: Digital Output Low Power



11b: Digital Output High Power

GPIO3_CONF

7:3

GPIO_SELECT

Specify the GPIO3 I/O signal, default setting digital

GND (see Table 57).

RESERVED

1:0

GPIO_MODE

GPIO3 Mode:



00b: Analog



01b: Digital Input



10b: Digital Output Low Power



11b: Digital Output High Power

SYNT3

7:5

PLL_CP_ISEL

Set the charge pump current according to the XTAL

frequency (see Table 34).

Synthesizer band select. This parameter selects the

out-of loop divide factor of the synthesizer:



0: 4, band select factor for high band



1: 8, band select factor for middle band (see

Section 5.3.1).

3:0

SYNT[27:24]

MSB bits of the PLL programmable divider (see

Section 5.3.1).

SYNT2

7:0

SYNT[23:16]

Intermediate bits of the PLL programmable divider

(see Section 5.3.1).

SYNT1

7:0

SYNT[15:8]

Intermediate bits of the PLL programmable divider

(see Section 5.3.1).

SYNT0

7:0

SYNT[7:0]

LSB bits of the PLL programmable divider (see

Section 5.3.1).

IF_OFFSET_ANA

7:0

IF_OFFSET_ANA

Intermediate frequency setting for the analog RF

synthesizer, default: 300 kHz (see Equation 11).

IF_OFFSET_DIG

7:0

IF_OFFSET_DIG

Intermediate frequency setting for the digital shift-to-

baseband circuits, default: 300 kHz (see Equation 11).

CHSPACE

7:0

CH_SPACE

Channel spacing setting (see Equation 3).

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