S2-LPQTR datasheet(45/90 Pages) STMICROELECTRONICS

45 / 90 page

S2-LP

Block description

DocID029944 Rev 1

45/90

Figure 8: Threshold in FIFO

The TX FIFO has two programmable thresholds (see figure above). An interrupt event

occurs when the data in the TX FIFO reaches any of these thresholds. The first threshold is

the “FIFO Almost Full” threshold, TX_AF_THR registers. The value in this field corresponds

to the desired threshold value in number of bytes + 2. When empty locations (free) amount

inside the TX FIFO reaches this threshold limit, an interrupt to the MCU is generated so it

can send a TX command to transmit the contents of the TX FIFO. The second threshold for

TX is the “FIFO Almost Empty” threshold, TX_AE_THR register. When the data being

shifted out of the TX FIFO reaches the Almost Empty threshold, an interrupt will be

generated also. The MCU could to switch out of TX mode or fill new data into the TX FIFO.

The RX FIFO has two programmable thresholds (see figure above). The first threshold is

the “FIFO Almost Full” threshold, RX_AF_THR0 registers. The value in this register

corresponds to the desired threshold value in number of bytes. When empty locations

(free) amount inside the RX FIFO reaches this threshold limit, an interrupt will be generated

to the MCU. The MCU should then start to read the data from the RX FIFO. The second

threshold for RX is the “FIFO Almost Empty” threshold, RX_AE_THR register. When the

data being shifted out of the RX FIFO reaches the Almost Empty threshold, an interrupt will

be generated also. The MCU will need to switch on RX mode to fill with new data the RX

FIFO or stop to read after the number of byte indicated by the RX_AE_THR register.

In order to enable the RX_FIFO thresholds interrupts, the bit FIFO_GPIO_OUT_MUX_SEL

(PROTOCOL2 register) must be set to 1. To enable the TX_FIFO thresholds interrupts the

FIFO_GPIO_OUT_MUX_SEL must be set to 0.

The FIFO controller will detect overflow or underflow in the RX FIFO and overflow or

underflow in the TX FIFO. It is the responsibility of the MCU to avoid TX FIFO overflow

since the MCU only can decide to writing on the TX FIFO. A TX FIFO overflow will result in

an error in the TX FIFO content, while an underflow results in the continuous transmission

of the last byte stored in the TX FIFO. Likewise, when reading the RX FIFO the MCU must

avoid reading the RX FIFO after its empty condition is reached, since a RX FIFO underflow

will result in an error in the data read out of the RX FIFO.

When an overflow or an underflow is detected, the MCU has to issue a SABORT and a

FLUSHTXFIFO/ FLUSHRXFIFO command before resuming the normal transceiver activity.

For each FIFO, when one of these errors is detected an interrupt will be generated to the

MCU.

S2-LPQTR 数据表(PDF) 45 Page - STMicroelectronics

S2-LPQTR 数据表(HTML) 45 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载