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OMAP3530ECBBA 数据表(PDF) 222 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 222 Page - Texas Instruments |
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222 / 265 page  mmx_txen_n mmx_txdat mmx_txse0 FSUT21 FSUT19 FSUT20 FSUT17 FSUT17 FSUT18 FSUT18 FSUT22 FSUT23 Transmit Receive 030-085 OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 6-92. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode (continued) TIMING CONDITION PARAMETER VALUE UNIT CLOAD Output load capacitance 15 pF Table 6-93. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 3-pin Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSUT17 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low 14 14 ns together during transition FSUT18 td(DAT,SE0) Time duration, mmx_tsdat and mmx_txse0 high 8 8 ns together during transition Table 6-94. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 3-pin Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX FSUT19 td(TXENH-DATV) Delay time, mmx_txen_n high to mmx_txdat valid 81.8 84.8 81.8 84.8 ns FSUT20 td(TXENH-SE0V) Delay time, mmx_txen_n high to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns FSUT21 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 1.5 1.5 ns transition FSUT22 td(DATI-TXENL) Delay time, mmx_txdat invalid mmx_txen_n low 81.8 81.8 ns FSUT23 td(SE0I-TXENL) Delay time, mmx_txse0 invalid mmx_txen_n low 81.8 81.8 ns tR(dat) Rise time, mmx_txdat 4 4 ns tF(dat) Fall time, mmx_txdat 4 4 ns tR(se0) Rise time, mmx_txse0 4 4 ns tF(se0) Fall time, mmx_txse0 4 4 ns tR(do) Rise time, mmx_txse0 4 4 ns tF(do) Fall time, mmx_txse0 4 4 ns In mmx, x is equal to 0, 1, or 2. Figure 6-48. Low-/Full-Speed USB – Bidirectional TLL 3-pin Mode 6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing In addition to the full-speed USB controller, a high-speed (HS) USB OTG controller is instantiated inside OMAP3530/25. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2, and 3. • Port 0: – 12-bit slave mode (SDR) • Port 1 and port 2: – 12-bit master mode (SDR) – 12-bit TLL master mode (SDR) – 8-bit TLL master mode (DDR) 222 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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