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OMAP3530ECBBA 数据表(PDF) 50 Page - Texas Instruments

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部件名 OMAP3530ECBBA
功能描述  Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBA 数据表(HTML) 50 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
mcspi3_somi
2
IO
dss_data2
3
IO
gpio_90
4
IO
safe_mode
7
-
AC25
NA
dss_data22
0
O
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
mcspi3_cs1
2
O
dss_data4
3
IO
gpio_92
4
IO
safe_mode
7
-
AB25
NA
dss_data23
0
O
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
dss_data5
3
IO
gpio_93
4
IO
safe_mode
7
-
G25
NA
dss_pclk
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_66
4
IO
hw_dbg12
5
O
safe_mode
7
-
J2
NA
gpmc_a1
0
O
L
L
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_34
4
IO
safe_mode
7
-
H1
NA
gpmc_a2
0
O
L
L
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_35
4
IO
safe_mode
7
-
H2
NA
gpmc_a3
0
O
L
L
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_36
4
IO
safe_mode
7
-
G2
NA
gpmc_a4
0
O
L
L
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_37
4
IO
safe_mode
7
-
F1
NA
gpmc_a5
0
O
L
L
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_38
4
IO
safe_mode
7
-
F2
NA
gpmc_a6
0
O
H
H
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_39
4
IO
safe_mode
7
-
E1
NA
gpmc_a7
0
O
H
H
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_40
4
IO
safe_mode
7
-
E2
NA
gpmc_a8
0
O
H
H
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
gpio_41
4
IO
safe_mode
7
-
D1
NA
gpmc_a9
0
O
H
H
7
vdds
Yes
4
(4)
PU100/
LVCMOS
PD100
sys_ndmareq
1
I
2
gpio_42
4
IO
safe_mode
7
-
(4)
The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
50
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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