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OMAP3530ECBBA 数据表(PDF) 58 Page - Texas Instruments

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部件名 OMAP3530ECBBA
功能描述  Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBA 数据表(HTML) 58 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
R2
NA
uart1_rts
0
O
L
L
7
vdds
Yes
4
(13)
PU100/
LVCMOS
PD100
gpio_149
4
IO
safe_mode
7
-
H3
NA
uart1_rx
0
I
L
L
7
vdds
Yes
4
(13)
PU100/
LVCMOS
PD100
mcbsp1_clkr
2
IO
mcspi4_clk
3
IO
gpio_151
4
IO
safe_mode
7
-
L4
NA
uart1_tx
0
O
L
L
7
vdds
Yes
4
(13)
PU100/
LVCMOS
PD100
gpio_148
4
IO
safe_mode
7
-
Y24
NA
uart2_cts
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_dx
1
IO
gpt9_pwm_e
2
IO
vt
gpio_144
4
IO
safe_mode
7
-
AA24
NA
uart2_rts
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_dr
1
I
gpt10_pwm_
2
IO
evt
gpio_145
4
IO
safe_mode
7
-
AD21
NA
uart2_rx
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_fsx
1
IO
gpt8_pwm_e
2
IO
vt
gpio_147
4
IO
safe_mode
7
-
AD22
NA
uart2_tx
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_clkx
1
IO
gpt11_pwm_
2
IO
evt
gpio_146
4
IO
safe_mode
7
-
F23
NA
uart3_cts_rct
0
IO
H
H
7
vdds
Yes
4
PU100/
LVCMOS
x
PD100
gpio_163
4
IO
safe_mode
7
-
F24
NA
uart3_rts_sd
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_164
4
IO
safe_mode
7
-
H24
NA
uart3_rx_irrx
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_165
4
IO
safe_mode
7
-
G24
NA
uart3_tx_irtx
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
gpio_166
4
IO
safe_mode
7
-
J23
NA
hdq_sio
0
IOD
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
sys_altclk
1
I
58
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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