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OMAP3530ECBBA 数据表(PDF) 52 Page - Texas Instruments

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部件名 OMAP3530ECBBA
功能描述  Applications Processors
PDF  265 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBA 数据表(HTML) 52 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
K2
NA
gpmc_nbe0_
0
O
L
0
0
vdds
Yes
4
(5)
PU100/
LVCMOS
cle
PD100
gpio_60
4
IO
safe_mode
7
-
J1
NA
gpmc_nbe1
0
O
L
L
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_61
4
IO
safe_mode
7
-
AD8
AA8
gpmc_ncs0
0
O
1
1
0
vdds
No
4
(5)
NA
LVCMOS
AD1
W1
gpmc_ncs1
0
O
H
1
0
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_52
4
IO
safe_mode
7
-
A3
NA
gpmc_ncs2
0
O
H
H
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
gpio_53
4
IO
safe_mode
7
-
B6
NA
gpmc_ncs3
0
O
H
H
7
vdds
Yes
4
(5)
PU100/
LVCMOS
PD100
sys_ndmareq
1
I
0
gpio_54
4
IO
safe_mode
7
-
B4
NA
gpmc_ncs4
0
O
H
H
7
vdds
Yes
4
(6)
PU100/
LVCMOS
PD100
sys_ndmareq
1
I
1
mcbsp4_clkx
2
IO
gpt9_pwm_e
3
IO
vt
gpio_55
4
IO
safe_mode
7
-
C4
NA
gpmc_ncs5
0
O
H
H
7
vdds
Yes
4
(6)
PU100/
LVCMOS
PD100
sys_ndmareq
1
I
2
mcbsp4_dr
2
I
gpt10_pwm_
3
IO
evt
gpio_56
4
IO
safe_mode
7
-
B5
NA
gpmc_ncs6
0
O
H
H
7
vdds
Yes
4
(6)
PU100/
LVCMOS
PD100
sys_ndmareq
1
I
3
mcbsp4_dx
2
IO
gpt11_pwm_
3
IO
evt
gpio_57
4
IO
safe_mode
7
-
C5
NA
gpmc_ncs7
0
O
H
H
7
vdds
Yes
4
(6)
PU100/
LVCMOS
PD100
gpmc_io_dir
1
O
mcbsp4_fsx
2
IO
gpt8_pwm_e
3
IO
vt
gpio_58
4
IO
safe_mode
7
-
N2
L2
gpmc_noe
0
O
1
1
0
vdds
No
4
(6)
NA
LVCMOS
(6)
The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the
selected mode.
52
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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