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OMAP3530ECBBA 数据表(PDF) 252 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 252 Page - Texas Instruments |
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252 / 265 page  sdti_clk sdti_txd[3:0] Header Header Ad[7:4] Ad[3:0] Da[15:12] Da[11:8] Da[7:4] Da[3:0] SD1 SD2 SD3 SD3 030-112 OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 6-146. System Debug Trace Interface Switching Characteristics – Single-Edge Mode (continued) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX tF(CLK) Fall time, sdti_txd[3:0] 5 5 ns Figure 6-71. System Debug Trace Interface – Single-Edge Mode 6.8.3 JTAG Interfaces OMAP3530/25 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define the timing requirements for several tools used to test the OMAP3530/25 processors as: • Free running clock tool, like XDS560 and XDS510 tools • Adaptive clock tool, like RealView® ICE tool and Lauterbach™ tool 6.8.3.1 JTAG – Free Running Clock Mode Table 6-148 and Table 6-149 assume testing over the recommended operating conditions and electrical characteristic conditions (see Figure 6-72). Table 6-147. JTAG Timing Conditions – Free Running Clock Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 5 ns tF Input signal fall time 5 ns Output Conditions CLOAD Output load capacitance 30 pF Table 6-148. JTAG Timing Requirements – Free Running Clock Mode(1) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX JT4 tc(tck) Cycle time(2), jtag_tck period 25 33 ns JT5 tw(tckL) Typical pulse duration, jtag_tck low 0.5*P(3) 0.5*P(3) ns JT6 tw(tckH) Typical pulse duration, jtag_tck high 0.5*P(3) 0.5*P(3) ns tdc(tck) Duty cycle error, jtag_tck –1250 1250 –1667 1667 ps tj(tck) Cycle jitter(4), jtag_tck –1250 1250 –1667 1667 ps JT7 tsu(tdiV-rtckH) Setup time, jtag_tdi valid before jtag_rtck high 1.8 1.8 ns JT8 th(tdiV-rtckH) Hold time, jtag_tdi valid after jtag_rtck high 0.7 1 ns JT9 tsu(tmsV-rtckH) Setup time, jtag_tms valid before jtag_rtck high 1.8 1.8 ns JT10 th(tmsV-rtckH) Hold time, jtag_tms valid after jtag_rtck high 0.7 1 ns JT12 tsu(emuxV-rtckH) Setup time, jtag_emux(5) valid before jtag_rtck 14.6 19.8 ns high JT13 th(emuxV-rtckH) Hold time,jtag_emux(5) valid after jtag_rtck high 2 2.7 ns (1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) Related with the input maximum frequency supported by the JTAG module. (3) P = jtag _tck period in ns. (4) Maximum cycle jitter supported by jtag _tck input clock. (5) x = 0 to 1 252 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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