STMPE321 datasheet(21/40 Pages) STMICROELECTRONICS

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STMPE321

Interrupt controller module

Doc ID 15791 Rev 3

21/40

GPIO_INT_EN

GPIO interrupt enable registerI

Address:

0x0B, 0x0C

Type:

R/W

Reset:

0x00

Description:

The GPIO interrupt enable register is used to enable the interruption from a particular

GPIO interrupt source to the host. The IEg[2:0] bits and the interrupt enable mask bits

correspond to the GPIO[2:0] pins.

GPIO_INT_STA

GPIO interrupt status register

Address:

0x0D, 0x0E

Type:

R/W

Reset:

0x00

Description:

The GPIO interrupt status register LSB monitors the status of the interruption from a

particular GPIO pin interrupt source to the host. Regardless of whether or not the

IEGPIOR bits are enabled, the INT_STA_GPIO_LSB bits are still updated. The

ISG[2:0] bits are the interrupt status bits correspond to the GPIO[2:0] pins.

543

RESERVED

IEG

[7:3] RESERVED

[2:0] IEG[2:0]

Interrupt enable GPIO mask (where x = 2 to 0)

Writing a ‘1’ to the IE[x] bit enables the interruption to the host.

543

ISG

[7:0] ISG[x]:

Interrupt status GPIO (where x = 2 to 0)

Read:

Interrupt status of the GPIO[x]. Writing ‘1’ clears a bit. Writing ‘0’ has no effect.

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