PC87303 datasheet(13/114 Pages) NSC

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10 Pin Description (Continued)

TABLE 1-1 Pin Descriptions (Alphabetical)

(Continued)

Symbol

Function

IRQ5

Interrupt 5

Active high output that indicates a parallel port interrupt When enabled this bit follows

the ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port

address is designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this

signal is TRI-STATE

This pin is IO only when ECP is enabled IRQ5 is configured and bit 6 of PCR is 1 (See ADRATE0

for further information)

IRQ6

Interrupt 6

Active high output to signal the completion of the execution phase for certain FDC

commands Also used to signal when a data transfer is ready during a Non-DMA operation When in

PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode IRQ6 is

always enabled and bit D3 of the DOR is reserved

IRQ7

Interrupt 7

Active high output that indicates a parallel port interrupt When enabled this bit follows

the ACK signal input When bit 4 in the parallel port Control Register is set and the parallel port

address is designated as shown in Table 2-5 this interrupt is enabled When it is not enabled this

signal is TRI-STATE

This pin is IO only when ECP is enabled IRQ7 is configured and bit 6 of PCR is 1 For ECP

operation refer to the interrupt ECP Section 7111

IRQ8

Interrupt 8

Real-Time Clock interrupt request output This is an open-drain output

KBCLK

Keyboard Clock

output

KBDAT

Keyboard Data

output

MCLK

Mouse Clock

output

MDAT

Mouse Data

output

Master Reset

Active high input that resets the controller to the idle state and resets all disk

interface outputs to their inactive states The DOR DSR CCR Mode command Configure

command and Lock command parameters are cleared to their default values The Specify

command parameters are not affected The Configuration Registers are set to their selected default

values

MTR01

75 72

Motor Select 01

These are the motor enable lines for drives 0 and 1 and are controlled by bits

D7 – D4 of the Digital Output register They are active low outputs They are encoded with

information to control four FDDs when bit 4 of the Function Enable Register (FER) is set MTR0

exchanges logical motor values with MTR1 when bit 4 of FCR is set (See DR01 )

MSEN01

83 82

Media Sense

These pins are Media Sense input pins when bit 0 of FCR is 0 Each pin has a 40 kX

internal pull-up resistor When bit 0 of FCR is 1 these pins are Data Rate output pins and the pull-

up resistors are disabled (See DRATE01 for further information)

P10 – P17

141 – 148

IO Port

Quasi-bidirectional port for general purpose input and output

P20 – P27

151 – 158

IO Port

Quasi-bidirectional port for general purpose input and output

PD0 – 7

134 – 131

Parallel Port Data

These bidirectional pins transfer data to and from the peripheral data bus and

the parallel port Data Register These pins have high current drive capability (See DC Electrical

129 – 126

Characteristics)

PDACK

Printer DMA Acknowledge

Active low input to acknowledge a connected printer’s DMA request

and enable the RD and WR inputs during a DMA transfer This input is valid only in Enhanced

Capabilities Port (ECP) mode

PDRQ

Printer DMA Request

Active high output which signals the DMA controller that a printer data

transfer is required This pin is in TRI-STATE when ECP is disabled (PCR2 e 0) or when it is

configured without DMA (PMC3 e 0) This output is valid only in ECP mode

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