PC87303 datasheet(21/114 Pages) NSC

21 / 114 page

20 Configuration Registers (Continued)

25 BASE CONFIGURATION REGISTERS

251 Function Enable Register (FER Index 00h)

This register enables and disables major chip functions Dis-

abled functions have their clocks automatically powered

down but the data in their registers remains intact It also

selects whether the FDC and the IDE controller is located at

their primary or secondary address

Bit 0

When this bit is one the parallel port can be accessed

at the address specified in the FAR

Bit 1

When this bit is one UART1 can be accessed at the

address specified in the FAR When this bit is zero

access to UART1 is blocked and it is in power-down

mode The UART1 registers retain all data in power

down mode

Caution

Any UART1 interrupt that is enabled and

active or becomes active after UART1 is disabled as-

serts the associated IRQ pin when UART1 is dis-

abled If disabling UART1 via software clear the IRQ

Enable bit (MCR3) to zero before clearing FER 1

This is not an issue after reset because MCR3 is zero

until it is written

Bit 2

When this bit is one UART2 can be accessed at the

address specified in the FAR When this bit is zero

access to UART2 is blocked and it is in power-down

mode The UART2 registers retain all data in power

down mode

Caution

Any UART2 interrupt that is enabled and

active or becomes active after UART2 is disabled as-

serts the associated IRQ pin when UART1 is disabled

If disabling UART2 via software clear the IRQ En-

able bit (MCR3) to zero before clearing FER1 This is

not an issue after reset because MCR3 is zero until it

is written

Bit 3

When this bit is one the FDC can be accessed at the

address specified in the FER bits When this bit is

zero access to the FDC is blocked and it is in power-

down mode The FDC registers retain all data in pow-

er down mode

Bit 4

When this bit is zero the PC87303 can control two

floppy disk drives directly without an external decod-

er When this bit is one the two drive select signals

and two motor enable signals from the FDC are en-

coded so that four floppy disk drives can be con-

trolled (see Table 2-3 and

Figure 2-2 ) Controlling

four FDDs requires an external decoder The pin

states shown in Table 2-3 are a direct result of the bit

patterns shown All other bit patterns produce pin

states that should not be decoded to enable any

drive or motor

Bit 5

This bit selects the primary or secondary FDC ad-

dress (See Table 2-4)

Bit 6

When this bit is a one the IDE drive interface can be

accessed at the address specified by FER bit 7

When it is zero bit 0 of PMC determines whether the

HCS01 pins are inactive or in TRI-STATE IDEHI

and IDEHLO are inactive and IDED7 is in TRI-

STATE

Bit 7

This bit selects the primary or secondary IDE ad-

dress (See Table 2-4)

TABLE 2-3 Encoded Drive and Motor Pin Information (FER 4 e 1)

Digital Output Register

Drive Control Pins

Decoded Functions

MTR1

MTR0

DR1

DR0

XXX

(Note)

Activate Drive 0 and Motor 0

(Note)

Activate Drive 1 and Motor 1

(Note)

Activate Drive 2 and Motor 2

(Note)

Activate Drive 3 and Motor 3

XXX

(Note)

Activate Drive 0 and Deactivate Motor 0

(Note)

Activate Drive 1 and Deactivate Motor 1

(Note)

Activate Drive 2 and Deactivate Motor 2

(Note)

Activate Drive 3 and Deactivate Motor 3

Note

When FER4 e 1 MTR1 presents a pulse that is the inverted image of the IOW strobe This inverted pulse is active whenever an IO write to address 3F2h or

372h takes place This pulse is delayed by 25 ns–80 ns after the leading edge of IOW and its leading edge can be used to clock data into an external latch (eg

74LS175) Address 3F2h is used if the FDC is located at the primary address (FER5 e 0) and address 372h is used if the FDC is located at the secondary address

(FER5 e 1)

TLC12074 – 85

Hex Buffers

ICC e 40 mA

open collector

FIGURE 2-2 PC87303 Four Floppy Drive Circuit

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