PC87303 datasheet(23/114 Pages) NSC

23 / 114 page

20 Configuration Registers (Continued)

Bit 3

Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378 – 37Fh

(LPTB) This bit is a ‘‘don’t care’’ when the parallel

port address is 3BC – 3BEh (LPTA) or 278 – 27Fh

(LPTC)

Bit 4

Setting this bit puts UART1 into a test mode which

causes its Baud Out clock to be present on its SOUT1

pin if the Line Control Register bit 7 is set to 1

Bit 5

Setting this bit puts UART2 into a test mode which

causes its Baud Out clock to be present on its SOUT2

pin if the Line Control Register bit 7 is set to 1

Bit 6

Setting this bit to a 1 prevents all further write access-

es to the Configuration Registers Once it is set by

software it can only be cleared by a hardware reset

After the initial hardware reset it is 0

Bit 7

When not in EPP or ECP modes this bit controls

CompatibleExtended mode thus controlling Pulse

Level interrupt

Set this bit to 0 for Compatible mode Pulse Interrupt

Set this bit to 1 for Extended mode Level Interrupt

Note

Parallel port interrupt (PulseLevel) in EPP and ECP modes is

always pulse

In EPP mode this bit selects RegularAutomatic bi-di-

rectional mode thus selecting the direction control

method

Set this bit to 0 for Automatic mode Host RD and WR

signals control the direction

Set this bit to 1 for Regular mode bit 5 of CTR con-

trols the direction

After hardware reset this bit is 0

254 Function Control Register (FCR Index e 03h)

This register determines several pin options

It selects between Data Rate output and automatic media

sense inputs and between IDENT or IDEACK inputs for

DMA control of IDE

For Enhanced Parallel Port it enables the ZWS option

On reset the FCR 2 – 7 bits are cleared to 0

Bit 0

Media SenseData Rate select bit When this bit is

0 the MSEN0 – 1 pins are Media Sense inputs

When this bit is 1 the DRATE0-1 pins are Data

Rate outputs VLD0 pin is sampled during reset to

this bit When ths bit is 0 bits 5 – 7 of TDR are valid

When this bit is 1 bits 2 – 7 of TDR are TRI-STATE

during read When bit 2 of ASC Register is 1 TDR is

not controlled by this bit

Bit 1

IDENTIDEACK select bit When this bit is 0 the

IDENT pin is used and the IDE DMA is disabled

When this bit is 1 the IDE DMA is enabled and the

IDENT input is assumed to be 1

Bit 2

Reserved

Bit 3

Parallel Port Floating Control bit

When this bit is 0 there is no software uncondition-

al float control This bit does not affect the parallel

port pins

When this bit is 1 the parallel port outputs are in

TRI-STATE and their pull-ups are disconnected

Bit 4

Logical Drive Exchange bit This bit allows software

to exchange the physical floppy-disk control sig-

nals assigned to drives 0 and 1 thus exchanging

the logical drives A and B

This is accomplished by exchanging control of the

DR0 and MTR0 pins with the DR1 and MTR1 pins

The result is undefined if this bit is set while bit 4 of

FER is 1 Table 2-9 shows the associations be-

tween the Configuration Register bit the Digital

Output Register bits (DRVSEL01 and MTR01) and

the drive and motor control pins (DR01 and

MTR01) When bit 2 of ASC Register is 1 the logi-

cal drive exchange function is controlled by bits 2

and 3 of TDR

TABLE 2-9 Logical Drive Exchange

FCR

Digital Output Register (FDC)

Asserted

Bit 4

MTR1

MTR0

DRVSEL1

DRVSEL0

FDC Pins

DR0

MTR0

DR1

MTR1

DR1

MTR1

DR0

MTR0

Bit 5

Zero Wait State enable bit If this bit is 1 ZWS is

driven low when the Enhanced Parallel Port

(EPP) or the ECP can accept a short host read

write-cycle otherwise the ZWS open drain output

is not driven EPP ZWS operation should be con-

figured when the system’s device is fast enough

to support it

Bits 6 7

Reserved Use Read Modified Write to change the

FCR register

255 Printer Control Register (PCR Index e 04h)

This register enables the EPP and ECP version modes and

interrupt options It also enables the RTC RAM write mask

bit On reset the PCR bits are cleared to 0

The parallel port mode is software configurable as follows

TABLE 2-10 Parallel Port Mode

Operation

FER

PTR

PCR

Mode

Bit 0

Bit 7

Bit 0

Bit 2

None

Compatible

1000

Extended

1100

EPP

ECP

Bit 0

EPP enable bit When this bit is 0 the EPP is dis-

abled and the EPP registers are not accessible

(access ignored)

When this bit is 1 and bit 2 of PCR is 0 the EPP is

enabled Note that the EPP should not be config-

ured with base address 3BCh

For further information refer to bit 5 of FCR

PC87303 数据表(PDF) 23 Page - National Semiconductor (TI)

PC87303 数据表(HTML) 23 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

PC87303 数据表(PDF) 23 Page - National Semiconductor (TI)

PC87303 数据表(HTML) 23 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载