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TNETV2666FIBZWT 数据表(PDF) 195 Page - Texas Instruments |
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TNETV2666FIBZWT 数据表(HTML) 195 Page - Texas Instruments |
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195 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 6.13.2 McBSP Electrical Data/Timing 6.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 6-40. Timing Requirements for McBSP(1) (see Figure 6-25) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT MIN MAX 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P(2) (3) ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P - 1(4) ns CLKR int 14 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low ns CLKR ext 4 CLKR int 6 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext 4 CLKR int 14 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext 4 CLKR int 3.5 8 th(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext 3 CLKX int 14 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext 4 CLKX int 6 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext 3 (1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10ns. (3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 195 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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