STUSB1602 datasheet(14/55 Pages) STMICROELECTRONICS

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Features description

STUSB1602

14/55

DocID028319 Rev 2

3.2.3

RX mode

RX mode is the default state of the BMC interface.

In this mode, the receiver listens to the connected CC line. It does not interface with the CC

line interfaces or the CC control logic.

When all data are detected and received on the CC line, according to the activity described

in the USB Power Delivery Standard, the BMC interface:

•

Drives the NSS signal low

•

Outputs the clock on the SCLK signal which is recovered from the BMC signal

•

Outputs recovered data (from the BMC signal) on the MOSI line to the connected MCU.

Data are valid on the SCLK falling edge and are sampled on this edge by the SPI/MSP

interface of the MCU.

When no more data are detected on the CC line, the NSS goes back to “high” which is its

default state. This indicates to the MCU that no more activity is present on the bus.

3.3

VBUS power path control

3.3.1

VBUS monitoring

The VBUS monitoring block supervises (from the VBUS_SENSE pin) the VBUS voltage on

the USB Type-C receptacle side.

It is used to check that the VBUS is within a valid voltage range:

•

To establish a valid source-to-sink connection according to USB Type-C standard

specifications.

•

To safely enable the VBUS power path through the VBUS_EN_SRC pin or

VBUS_EN_SNK pin depending on the power role.

It allows detection of unexpected VBUS voltage conditions such as under-voltage or

overvoltage relative to the valid VBUS voltage range. When such conditions occur, the

STUSB1602 reacts as follows:

•

At attachment, it prevents the source-to-sink connection and the VBUS power path

assertion.

•

After attachment, it deactivates the source-to-sink connection and disables the VBUS

power path. In source power role, the device goes into error recovery state. In Sink

power role, the device goes into unattached state.

The VBUS voltage value is adjusted automatically at attachment (vSafe5V) and via the MCU

at each PDO transition. Monitoring is then disabled during T_PDO_transition (i.e. the default

value of 300 ms is changed through NVM programming). Additionally, if a transition occurs

to a lower voltage, the discharge path is activated during this time.

The valid VBUS voltage range is defined from the VBUS nominal voltage by a high threshold

voltage and a low threshold voltage whose nominal values are respectively VBUS+5% and

VBUS-5%. The nominal threshold limits can be shifted by a fraction of VBUS from +1% to

+15% for the high threshold voltage and from -1% to -15% for the low threshold voltage.

This means the threshold limits can vary from VBUS+5% to VBUS+20% for the high limit and

from VBUS-5% to VBUS-20% for the low limit.

STUSB1602 数据表(PDF) 14 Page - STMicroelectronics

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