STUSB1602 datasheet(15/55 Pages) STMICROELECTRONICS

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STUSB1602

Features description

The threshold limits are preset by default in the NVM with different shift coefficients

depending on whether the device operates in source power role or in sink power role (see

Section 8.3: Electrical and timing characteristics). The threshold limits can be changed

independently through NVM programming (see Section 6: Start-up configuration) and also

by software during attachment through the I2C interface.

3.3.2

VBUS discharge

The monitoring block also handles the internal VBUS discharge path connected to the

VBUS_SENSE pin. The discharge path is activated at detachment, or when the device goes

into the error recovery state whatever the power role (see Section 3.8: Hardware fault

management).

The VBUS discharge path is enabled by default in the NVM and can be disabled through

NVM programming only (see Section 6: Start-up configuration). The discharge time duration

is also preset by default in the NVM (see Section 8.3: Electrical and timing characteristics).

The discharge time duration can be changed through NVM programming (see Section 6:

Start-up configuration) and also by software through the I2C interface.

3.3.3

VBUS power path assertion

The STUSB1602 can control the assertion of the VBUS power path on the USB Type-C port,

directly or indirectly, through the VBUS_EN_SRC and VBUS_EN_SNK pins according to the

system power role.

The tables below summarize the configurations and the conditions that determine the

electrical value of the VBUS_EN_SRC and VBUS_EN_SNK pins during system operation.

Table 6. Conditions for VBUS power path assertion in source power role

Electrical

value

Operation conditions

Comment

Type-C attached

state

VDD pin

monitoring

VBUS_SENSE pin

monitoring

VBUS_EN_SRC

Attached.SRC

UnorientedDebug

Accessory.SRC

OrientedDebug

Accessory.SRC

VDD > UVLO if

VDD_UVLO

enabled

and/or

VDD < OVLO if

VDD_OVLO

enabled

VBUS is within valid

voltage range if

VBUS _VALID_RANGE

enabled

VBUS > UVLO if

VBUS _VALID_RANGE

disabled

The signal is

asserted

only if all the

valid

operation

conditions

are met

HiZ

Any other state

VDD < UVLO if

VDD_UVLO

enabled

and/or

VDD > OVLO if

VDD_OVLO

enabled

VBUS is out of valid

voltage range if

VBUS _VALID_RANGE

enabled

VBUS < UVLO if

VBUS _VALID_RANGE

disabled

The signal is

de-asserted

when at

least one

non valid

operation

condition is

met

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