Application details

L6738A

22/32

Doc ID 18134 Rev 2

9

Application details

9.1

Compensation network

The control loop shown in Figure 9 is a voltage mode control loop. The output voltage is

regulated to the internal reference (when present, an offset resistor between FB node and

GND can be neglected in control loop calculation).

Error amplifier output is compared to the oscillator sawtooth waveform to provide a PWM

signal to the driver section. The PWM signal is then transferred to the switching node with

The converter transfer function is the small signal transfer function between the output of the

Figure 9.

PWM control loop

function ideally equal to -Z

Compensation goal is to close to the control loop assuring high DC regulation accuracy,

good dynamic performance and stability. To achieve this, the overall loop needs high DC

gain, high bandwidth and good phase margin.

High DC gain is achieved giving an integrator shape to compensation network transfer

has to cross the 0dB axis with -20dB/decade slope.

For example, Figure 10 shows an asymptotic bode plot of a type III compensation.

L

R

C

OUT

ESR

R

F

C

F

C

P

R

FB

C

S

OSC

V

IN

∆V

OSC

+

+

_

_

V

OUT

V

REF

Z

F

Z

FB

PWM

COMPARATOR

ERROR

AMPLIFIER

R

S