VIPER0P datasheet(30/36 Pages) STMICROELECTRONICS

30 / 36 page

Application information

VIPer0P

30/36

DocID028423 Rev 2

single "star point", placed close to the IC. Power ground traces should be connected

to the IC power ground, PGND. SGND and PGND are then to be connected to each

other with the shortest track as possible. The compensation network should be

connected to the COMP, maintaining the trace to SGND as short as possible. In case

of two layer PCB, it is a good practice to route signal traces on one PCB side and

power traces on the other side.



Filtering sensitive pins: some crucial points of the circuit need or may need filtering.

A small high-frequency bypass capacitor to SGND might be useful to get a clean bias

voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A

w ESL ceramic capacitor (a few hundreds pF up to 0.1 μF) should be connected

across VCC and SGND, placed as close as possible to the IC. With flyback

topologies, when the auxiliary winding is used, it is suggested to connect the VCC

capacitor on the auxiliary return and then to the main GND using a single track. In

case of nosy environment, it is strongly recommended to filter ON and OFF with small

ceramic capacitors (tens to hundreds pF) connected to SGND, in order to improve the

system noise immunity.



Keep power loops as confined as possible: minimize the area circumscribed by

current loops where high pulsed currents flow, in order to reduce its parasitic self-

inductance and the radiated electromagnetic field: this will greatly reduce the

electromagnetic interferences produced by the power supply during the switching. In a

flyback converter the most critical loops are: the one including the input bulk capacitor,

the power switch, the power transformer, the one including the snubber, the one

including the secondary winding, the output rectifier and the output capacitor. In a

buck converter the most critical loop is the one including the input bulk capacitor, the

power switch, the power inductor, the output capacitor and the free-wheeling diode.



Reduce line lengths: any wire will act as an antenna. With the very short rise times

exhibited by EFT pulses, any antenna has the capability of receiving high voltage

spikes. By reducing line lengths, the level of radiated energy that is received will be

reduced, and the resulting spikes from electrostatic discharges will be lower. This will

also keep both resistive and inductive effects to a minimum. In particular, all of traces

carrying high currents, especially if pulsed (tracks of the power loops) should be as

short and fat as possible.



Optimize track routing: as levels of pickup from static discharges are likely to be

greater closer to the extremities of the board, it is wise to keep any sensitive lines

away from these areas. Input and output lines will often need to reach the PCB edge

at some stage, but they can be routed away from the edge as soon as possible where

applicable. Since vias are to be considered inductive elements, it is recommended to

minimize their number in the signal path and avoid them when designing the power

path.



Improve thermal dissipation: an adequate copper area has to be provided under the

DRAIN pins as heat sink, while it is not recommended to place large copper areas on

the SGND and PGND.

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