STM32F098CC datasheet(17/128 Pages) STMICROELECTRONICS

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STM32F098CC STM32F098RC STM32F098VC

Functional overview

The I/O configuration can be locked if needed following a specific sequence in order to

avoid spurious writing to the I/Os registers.

3.8

Direct memory access controller (DMA)

The 12-channel general-purpose DMAs (seven channels for DMA1 and five channels for

DMA2) manage memory-to-memory, peripheral-to-memory and memory-to-peripheral

transfers.

The DMAs support circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers

(except TIM14), DAC and ADC.

3.9

Interrupts and events

3.9.1

Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4

priority levels.

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Closely coupled NVIC core interface

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail-chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.9.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 87

GPIOs can be connected to the 16 external interrupt lines.

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