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STM32L432KB 数据表(PDF) 136 Page - STMicroelectronics

部件名 STM32L432KB
功能描述  Batch acquisition mode
PDF  149 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32L432KB 数据表(HTML) 136 Page - STMicroelectronics

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Electrical characteristics
STM32L432KB STM3L432KC
136/149
DocID028798 Rev 2
Quad SPI characteristics
Unless otherwise specified, the parameters given in Table 77 and Table 78 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 20: General operating conditions, with the
following configuration:
Output speed is set to OSPEEDRy[1:0] = 11
Capacitive load C = 15 or 20 pF
Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 77. Quad SPI characteristics in SDR mode(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FCK
1/t(CK)
Quad SPI clock frequency
1.71 < VDD< 3.6 V, CLOAD = 20 pF
Voltage Range 1
--
40
MHz
1.71 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1
--
48
2.7 < VDD< 3.6 V, CLOAD = 15 pF
Voltage Range 1
--
60
1.71 < VDD < 3.6 V CLOAD = 20 pF
Voltage Range 2
--
26
tw(CKH)
Quad SPI clock high and
low time
fAHBCLK= 48 MHz, presc=0
t(CK)/2-2
-
t(CK)/2
ns
tw(CKL)
t(CK)/2
-
t(CK)/2+2
ts(IN)
Data input setup time
Voltage Range 1
2
-
-
Voltage Range 2
3.5
-
-
th(IN)
Data input hold time
Voltage Range 1
5
-
-
Voltage Range 2
6.5
-
-
tv(OUT)
Data output valid time
Voltage Range 1
-
1
5
Voltage Range 2
-
3
5
th(OUT)
Data output hold time
Voltage Range 1
0
-
-
Voltage Range 2
0
-
-
1. Guaranteed by characterization results.



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