Coding Law Selection

Bits “MA” and “IA” in

Table 2 permit the selection of µ255

coding or A-law coding, with or without even bit inversion.

Analog Loopback

Analog Loopback mode is entered by setting the “AL” and

“DL” bits in the Control Register as shown in

Table 2.Inthe

analog loopback mode, the Transmit input VF

from the input pin and internally connected to the VF

put, forming a loop from the Receive PCM Register back to

the Transmit PCM Register. The VF

and the programmed settings of the Transmit and Receive

gains remain unchanged, thus care must be taken to ensure

that overload levels are not exceeded anywhere in the loop.

Digital Loopback

Digital Loopback mode is entered by setting the “AL” and

“DL” bits in the Control Register as shown in

Table 2. This

mode provides another stage of path verification by enabling

data written into the Receive PCM Register to be read back

from that register in any Transmit time-slot at D

coding continues and analog output appears at VF

output can be disabled by programming ‘No Output’ in the

Receive Gain Register (see

Table 8).

INTERFACE LATCH DIRECTIONS

Immediately following power-on, all Interface Latches as-

sume they are inputs, and therefore all IL pins are in a high

impedance state. Each IL pin may be individually pro-

grammed as a logic input or output by writing the appropriate

instruction to the LDR, see

Table 1 and Table 3. For mini-

mum power dissipation, unconnected latch pins should be

programmed as outputs. For the TP3076, bits 2 and 3 should

always be programmed as “1” (outputs).

Bits L

the LDR with the L bits in the second byte set as follows:

TABLE 3. Byte 2 Functions of Latch Direction Register

Byte 2 Bit Number

76543210

L

0

L

1

L

2

L

3

11

X

X

L

IL Direction

0

Input

1

Output

X = Don’t Care

INTERFACE LATCH STATES

Interface Latches configured as outputs assume the state

determined by the appropriate data bit in the 2-byte instruc-

tion written to the Interface Latch Register (ILR) as shown in

Table 1 and Table 4. Latches configured as inputs will sense

the state applied by an external source, such as the

Off-Hook detect output of a SLIC. All bits of the ILR, i.e.

sensed inputs and the programmed state of outputs, can be

read back in the 2nd byte of a READ from the ILR.

It is recommended that during initialization, the state of IL

pins to be configured as outputs should be programmed first

followed immediately by the Latch Direction Register.

TABLE 4. Interface Latch Data Bit Order

Bit Number

76543210

D

0

D

1

D

2

D

3

D

4

D

5

XX

TABLE 5. Coding Law Conventions

µ255 Law

True A-Law with

A-Law without

Even Bit Inversion

Even Bit Inversion

MSB

LSB

MSB

LSB

MSB

LSB

V

10000000

10101010

111111111

V

11111111

11010101

100000000

11111111

01010101

000000000

V

00000000

00101010

011111111

Note 5: The MSB is always the first PCM bit shifted in or out of COMBO II.

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