Unless otherwise noted, limits printed in BOLD characters are guaranteed for V

+70˚C by correlation with 100% electrical testing at T

tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V

T

All timing parameters are measured at V

See Definitions and Timing Conventions section for test methods information.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PCM INTERFACE TIMING

High to Data Valid

Applies if FS

80

ns

BCLK Rising Edge in Non-Delayed Data

Mode Only

t

SDB

Setup Time, D

30

ns

Valid to BCLK Low

t

HBD

Hold Time, BCLK

15

ns

Low to D

SERIAL CONTROL PORT TIMING

f

CCLK

Frequency of CCLK

2048

kHz

t

WCH

Period of CCLK High

Measured from V

160

ns

t

WCL

Period of CCLK Low

Measured from V

160

ns

t

RC

Rise Time of CCLK

Measured from V

50

ns

t

FC

Fall Time of CCLK

Measured of V

50

ns

t

HCS

Hold Time, CCLK Low

CCLK1

10

ns

to CS Low

t

HSC

Hold Time, CCLK

CCLK8

100

ns

Low to CS High

t

SSC

Setup Time, CS

60

ns

Transition to CCLK Low

t

SSC0

Setup Time, CS

To Insure CO is Not Enabled

60

ns

Transition to CCLK High

for Single Byte

t

SDC

Setup Time, CI

50

ns

Data In to CCLK Low

t

HCD

Hold Time, CCLK

50

ns

Low to CO Invalid

t

DCD

Delay Time, CCLK High

Load = 100 pF Plus 2 LSTTL Loads

80

ns

to CO Data Out Valid

t

DSD

Delay Time, CS Low

Applies Only if Separate

80

ns

to CO Valid

CS Used for Byte 2

t

DDZ

Delay Time, CS or 9th CCLK

Applies to Earlier of CS

15

80

ns

High to CO High Impedance

High or 9th CCLK High

INTERFACE LATCH TIMING

t

SLC

Setup Time, IL to

Interface Latch Inputs Only

100

ns

CCLK 8 of Byte 1

t

HCL

Hold Tme, IL Valid from

50

ns

8th CCLK Low (Byte 1)

t

DCL

Delay Time CCLK8 of

Interface Latch Outputs Only

200

ns

Byte2toIL

C

Note 14: Applies only to MCLK Frequencies

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