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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HPC16003 数据表(PDF) 3 Page - National Semiconductor (TI) |
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HPC16003 数据表(HTML) 3 Page - National Semiconductor (TI) |
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3 / 36 page  20 MHz AC Electrical Characteristics (See Notes 1 and 4 and Figure 1 thru Figure 5 )VCC e 50V g10% unless otherwise specified TA e 0 Cto a70 C for HPC46083HPC46003 b40 Cto a85 C for HPC36083HPC36003 b40 Cto a105 C for HPC26083HPC26003 b55 Cto a 125 C for HPC16083HPC16003 Symbol and Formula Parameter Min Max Units Note fC CKI Operating Frequency 2 20 MHz tC1 e 1fC CKI Clock Period 50 500 ns tCKIH CKI High Time 225 ns tCKIL CKI Low Time 225 ns tC e 2fC CPU Timing Cycle 100 ns tWAIT e tC CPU Wait State Period 100 ns tDC1C2R Delay of CK2 Rising Edge after 0 55 ns (Note 2) CKI Falling Edge tDC1C2F Delay of CK2 Falling Edge after 0 55 ns (Note 2) CKI Falling Edge fU e fC 8 External UART Clock Input Frequency 25 MHz fMW External MICROWIREPLUS 125 MHz Clock Input Frequency fXIN e fC 22 External Timer Input Frequency 091 MHz tXIN e tC Pulse Width for Timer Inputs 100 ns tUWS MICROWIRE Setup TimeMaster 100 ns Slave 20 tUWH MICROWIRE Hold TimeMaster 20 ns Slave 50 tUWV MICROWIRE Output Valid TimeMaster 50 ns Slave 150 tSALE e tC a 40 HLD Falling Edge before ALE Rising Edge 115 ns tHWP e tC a 10 HLD Pulse Width 110 ns tHAE e tC a 100 HLDA Falling Edge after HLD Falling Edge 200 ns (Note 3) tHAD e tC a 85 HLDA Rising Edge after HLD Rising Edge 160 ns tBF e tC a 66 Bus Float after HLDA Falling Edge 116 ns (Note 5) tBE e tCa 66 Bus Enable after HLDA Rising Edge 116 ns (Note 5) tUAS Address Setup Time to Falling Edge of URD 10 ns tUAH Address Hold Time from Rising Edge of URD 10 ns tRPW URD Pulse Width 100 ns tOE URD Falling Edge to Output Data Valid 0 60 ns tOD Rising Edge of URD to Output Data Invalid 5 35 ns (Note 6) tDRDY RDRDY Delay from Rising Edge of URD 70 ns tWDW UWR Pulse Width 40 ns tUDS Input Data Valid before Rising Edge of UWR 10 ns tUDH Input Data Hold after Rising Edge of UWR 20 ns tA WRRDY Delay from Rising Edge of UWR 70 ns This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2 clock 3 |
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