HPC16003 datasheet(4/36 Pages) NSC

4 / 36 page

20 MHz

AC Electrical Characteristics

(See Notes 1 and 4 and

Figure 1 thru Figure 5 )VCC e 50V g10% unless otherwise specified TA e 0 Cto a70 C for

HPC46083HPC46003 b40 Cto a85 C for HPC36083HPC36003 b40 Cto a105 C for HPC26083HPC26003 b55 Cto

125 C for HPC16083HPC16003 (Continued)

Symbol and Formula

Parameter

Min

Max

Units

Note

tDC1ALER

Delay from CKI Rising

(Notes 1 2)

Edge to ALE Rising Edge

tDC1ALEF

Delay from CKI Rising

(Notes 1 2)

Edge to ALE Falling Edge

tDC2ALER e

Delay from CK2 Rising

(Note 2)

Edge to ALE Rising Edge

tDC2ALEF e

Delay from CK2 Rising

(Note 2)

Edge to ALE Rising Edge

tLL e

tC b 9

ALE Pulse Width

tST e

tC b 7

Setup of Address Valid

before ALE Falling Edge

tVP e

tC b 5

Hold of Address Valid

after ALE Falling Edge

tARR e

tC b 5

ALE Falling Edge to RD Falling Edge

tACC e tC a WS b 55

Data Input Valid after

145

(Note 6)

Address Output Valid

tRD e

tC a WS b 65

Data Input Valid after

RD Falling Edge

tRW e

tC a WS b 10

RD Pulse Width

140

tDR e

tC b 15

Hold of Data Input Valid

060

after RD Rising Edge

tRDA e tC b 15

Bus Enable after RD Rising Edge

tARW e

tC b 5

ALE Falling Edge to

WR Falling Edge

tWW e

tC a WS b 15

WR Pulse Width

160

tV e

tC a WS b 5

Data Output Valid before

145

WR Rising Edge

tHW e

tC b 5

Hold of Data Valid after

WR Rising Edge

tDAR e

tC a WS b 50

Falling Edge of ALE

to Falling Edge of RDY

tRWP e tC

RDY Pulse Width

100

Note

CL e 40 pF

Note 1

These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall

times (tCKIR and TCKIL) on CKI input less than 25 ns

Note 2

Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either

CKI or CKO is connected to any external logic other than the passive components of the crystal circuit

Note 3

tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling

edge occurs later tHAE as long as (3tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait state and ready input

Note 4

WS (tWAIT) x (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC e 20 MHz with

one wait programmed

Note 5

Due to emulation restrictionsactual limits will be better

Note 6

This is guaranteed by design and not tested

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