HPC16003 datasheet(6/36 Pages) NSC

6 / 36 page

30 MHz

AC Electrical Characteristics

(See Notes 1 and 4 and

Figure 1 thru Figure 5 )VCC e 50V g10% unless otherwise specified TA e 0 Cto a70 C for

HPC46083HPC46003 b40 Cto a85 C for HPC36083HPC36003 b40 Cto a105 C for HPC26083HPC26003 b55 Cto

125 C for HPC16083HPC16003 (Continued)

Symbol and Formula

Parameter

Min

Max

Units

Notes

tDC1ALER

Delay from CKI Rising Edge to ALE Rising Edge

(Notes 1 2)

tDC1ALEF

Delay from CKI Rising Edge to ALE Falling Edge

(Notes 1 2)

tDC2ALER e

tC a 20

Delay from CK2 Rising Edge to ALE Rising Edge

(Note 2)

tDC2ALEF e

tC a 20

Delay from CK2 Falling Edge to ALE Falling Edge

(Note 2)

tLL e

tC b 9

ALE Pulse Width

tST e

tC b 7

Setup of Address Valid before ALE Falling Edge

tVP e

tC b 5

Hold of Address Valid after ALE Falling Edge

tARR e

tC b 5

ALE Falling Edge to RD Falling Edge

tACC e tC a WS b 32

Data Input Valid after Address Output Valid

100

(Note 6)

tRD e

tC a WS b 39

Data Input Valid after RD Falling Edge

tRW e

tC a WS b 14

RD Pulse Width

tDR e

tC b 15

Hold of Data Input Valid after RD Rising Edge

tRDA e tC b 15

Bus Enable after RD Rising Edge

tARW e

tC b 5

ALE Falling Edge to WR Falling Edge

tWW e

tC a WS b 15

WR Pulse Width

101

tV e

tC a WS b 5

Data Output Valid before WR Rising Edge

tHW e

tC b 10

Hold of Data Valid after WR Rising Edge

tDAR e

tC a WS b 50

Falling Edge of ALE to Falling Edge of RDY

tRWP e tC

RDY Pulse Width

Note

CL e 40 pF

Note 1

These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO wih rise and fall

times (tCKIR and tCKIL) on CKI input less than 25 ns

Note 2

Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either

CKI or CKO is connected to any external logic other than the passive components of the crystal circuit

Note 3

tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling

edge occurs later tHAE as long as (3tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input

Note 4

WS tWAIT c (number of pre-programmed wait states) Minimum and maximum values are calculated from maximum operating frequency tC e 30 MHz

with one wait state programmed

Note 5

Due to emulation restrictionsactual limits will be better

Note 6

This is guaranteed by design and not tested

CKI Input Signal Characteristics

RiseFall Time

TLDD8801 – 35

Duty Cycle

TLDD8801 – 36

FIGURE 1 CKI Input Signal

TLDD8801 – 38

FIGURE 2 Input and Output for AC Tests

Note

AC testing inputs are driven at VIH for a logic ‘‘1’’ and VIL for a logic ‘‘0’’ Output timing measurements are made at 20V for a logic ‘‘1’’ and 08V for a logic

‘‘0’’

HPC16003 数据表(PDF) 6 Page - National Semiconductor (TI)

HPC16003 数据表(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载

链接网址

HPC16003 数据表(PDF) 6 Page - National Semiconductor (TI)

HPC16003 数据表(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表 下载

链接网址

数据表下载